A unified proposal for characteristic testing methods and figure of merit of 8‐kV/3.5‐kVA class light‐triggered thyristors

Power devices with high capability have been developed. 8‐kV/3.5‐kA‐class light‐triggered thyristors have the highest capability among power devices. These devices are used in the Kii Channel HVDC transmission system in Japan. In this paper, we report the extracted problems of conventional testing methods of 8‐kV/3.5‐kA‐class light‐triggered thyristors among manufacturers, and the proposed unified testing methods on the basis of element characteristics and operating conditions in the Kii Channel HVDC system. Furthermore, we propose a figure of merit for power devices for the practical use, and try to extract elements used at the Kii Channel HVDC system with small margins and low withstand capabilities. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(3): 61–70, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10024     

Relative importance of evaluation criteria for enterprise systems: a conjoint study

Abstract.  While a large body of research exists on the development and implementation of software, organizations are increasingly acquiring enterprise software packages [e.g. enterprise resource planning (ERP) systems] instead of custom developing their own software applications. To be competitive in the marketplace, software package development firms must manage the three-pronged trade-off between cost, quality and functionality. Surprisingly, prior research has made little attempt to investigate the characteristics of packaged software that influence management information system (MIS) managers' likelihood of recommending purchase. As a result, both the criteria by which MIS managers evaluate prospective packaged systems and the attributes that lead to commercially competitive ERP software products are poorly understood. This paper examines this understudied issue through a conjoint study. We focus on ERP systems, which are among the largest and most complex packaged systems that are purchased by organizations. In a conjoint study, 1008 evaluation decisions based on hypothetical ERP software package profiles were completed by managers in 126 organizations. The study represents the first empirical investigation of the relative importance that managers ascribe to various factors that are believed to be important in evaluating packaged software. The results provide important insights for both organizations that acquire such systems and those that develop them. The results show that functionality, reliability, cost, ease of use and ease of customization are judged to be important criteria, while ease of implementation and vendor reputation were not found to be significant. Functionality and reliability were found to be the most heavily weighted factors. We conclude the paper with a detailed discussion of the results and their implications for software acquisition and development practice.     

小型密闭压力容器测试系统重复性的研究

小型密闭压力容器测试（MCPVT）法是安全工程领域中近几年发展起来的、评价有机过氧化物及自反应物质受热分解反应激烈程度的新方法。pmax是MCPVT方法中用来表征自反应物质受热分解反应激烈程度的物理量之一。文中通过大量实验，研究了样品容器容积V、升温速率R及样品质量M对pmax重复性误差的影响，研究了一系列典型的有机过氧化物和自反应物质在标准实验条件下pmax重复性误差。结果表明，小型密闭压力容器测试系统重复性好，测试结果可靠，从而为MCPVT法最终成为国际上评价自反应物质受热分解反应激烈程度标准方法奠定了基础。     

储层石蜡沉积预测技术研究与应用

在油田开发过程中 ,由于油藏温度、压力等条件的变化 ,高含蜡原油在近井带容易产生石蜡沉积 ,堵塞地层孔隙或裂缝 ,严重影响油田开采 ,尤其对于低渗油田 ,伤害特别严重。文中应用理想溶液理论、质量守恒和能量守恒等基本原理 ,建立更符合油田实际情况的油藏中石蜡沉积预测数学模型 ,开发一套方便实用的油藏中石蜡沉积预测软件系统FPOS1 0。在此基础上 ,应用室内实验数据和现场数据对吉林新民油田油井石蜡沉积情况进行预测和现场拟合 ,确定新民油田临界石蜡沉积半径为 2 5m ,快速、准确地为现场清防蜡措施提供理论依据。     

罐装食品用电镀锡板的耐蚀性及其试验方法

综述了影响罐装食品用电镀锡板耐蚀性能的因素及其试验方法。     

软硬件协同设计语言System C在SoC设计中的应用

软硬件协同设计是未来VLSI设计的发展趋势.作为新的系统级VLSI设计标准,System C是一种通过类对象扩展的基于C/C++建模平台,支持系统级软硬件协同设计、仿真和验证.文章讨论了SystemC复杂芯片设计中的设计流程、设计优势,并给出具体设计实例.     

一种新型冰箱测试系统设计与应用

介绍了一种用于冰箱检测的新型测试系统，并在WIN98环境下用VB6．0实现该系统软件。该系统可以同时对四台冰箱的温度参数及其中一台冰箱的耗电量进行检测，该系统具有成本低，性能稳定的优点。     

复电阻率测井方法及其应用

复电阻率测井是以两频或多频测量地层电阻率的新方法 ,它可用来有效地识别油气层和确定水淹油层的水淹程度。简要介绍了复电阻率测井的测量原理、仪器设计。胜利油田 9口井的现场测井资料初步验证了该方法的可行性和有效性     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.