分段线性多开关时间次优控制系统的设计

提出一种新的时间次优控制系统的设计方法，利用分段线性近似构造了一个结构比较简单的开关函数，使系统在最大程度上逼近时间最优控制；同时在进入奇异振荡工作状态之前，自动由ＢＢＣ方式切换成线性控制，解决了切换试凑的困难。应用本文方法设计了某水下航行器航深时间次优控制系统并进行了仿真研究，仿真结果表明了本文方法的有效性。     

两类系统零解渐近稳定的充分条件

本文给出了非常系统数线性及非线性系统微分方程组在满足一定的条件下零解渐近稳定的充分条件。     

有限维子空间n-自反

本文讨论了L(H)中有限维子空间n-自反与其有限秩算子之间的关系,给出了关于n-自反的定理。     

一种基于程序结构和程序作用的复杂性度量

本文提出了一种将程序结构和它对环境状态的作用综合起来进行评估的程序复杂性度量方法.这一方法直观、易于理解、易于计算,并可以处理用其它度量方法无法解释的一些问题。     

线性系统的输出反馈解耦控制

建立了以闭环特征谱表达的关于线性系统输出反馈解耦的充要条件,并结合线性系统的特征结构配置结果给出了求解线性系统输出反馈解耦控制的一种参数化方法。该方法灵活、方便,且可顾及解耦系统的稳定性和性能要求。     

MSOR迭代法的收敛性

当线性方程组的系数矩阵A是严格对角占优阵、不可约弱对角占优阵、M阵、H阵和Stieltjes阵时,本文改进了M.Martins论文中MSOR迭代法收敛性的一些结果。     

DPSK信号多码元差分检测的低复杂度实现

本文提出了一种亲折ＤＰＳＫ信号的多码元差分检测方案,其复杂度随观察码元长度Ｎ仅呈线性上升,而Ｄｉｖｓａｌａｒ提出的最佳多码元差分检测实现复杂度随Ｎ呈指数上升＾［１］。分析与模拟结果表明：两者性能相仿。     

The Complexity of Modellability in Finite and Computable Signatures of a Constraint Logic for Head-Driven Phrase Structure Grammar

The SRL (speciate re-entrant logic) of King (1989) is a sound, complete and decidable logic designed specifically to support formalisms for the HPSG (head-driven phrase structure grammar) of Pollard and Sag (1994). The SRL notion of modellability in a signature is particularly important for HPSG, and the present paper modifies an elegant method due to Blackburn and Spaan (1993) in order to prove that

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs. This work was supported by the project PENED ’99 ED501 funded by GSRT of the Greek Ministry of Development, and the project PRENED ’99 KE 874 funded by the Research Committee of the Democritus University of Thrace. This work was partially sponsored by a scholarship from the Public Benefit Foundation of Alexander S. Onassis (Minas Dasygenis). Nikolaos Kroupis was born in Trikala in 1976. He receiver the engineering degree and Ms.C. degree in Department of Electrical and Computer Engineering from Democritous University of Thrace, Greece, in 2000 and 2002, respectively. Since 2002 he has been a Ph.D. student at the Laboratory of Electrical and Electronic Materials Technology. His research interests are in software/hardware co-design of embedded system for signal processing applications. Nikos D. Zervas received a Diploma in Electrical & Computer Engineering from University of Patras, Greece in 1997. He received the Ph.D. degree in the Department of Electrical and Computer Engineering of the same University in 2004. His research interests are in the area of high-level, power optimization techniques and methodologies for multimedia and telecommunication applications. He has received an award from IEEE Computer Society in the context of Low-Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop. Mr. Zervas is a member of the IEEE, ACM and of the Technical Chamber of Greece. Minas Dasygenis was born in Thessaloniki in 1976. He received his Diploma in Electrical and Computer Engineering in 1999, from the Democritus University of Thrace, Greece, and for his diploma Thesis he was honored by The Technical Chamber of Greece and Ericsson Hellas. In 2005, he received his PhD Degree from the Democritus University of Thrace. His research interests include low-power VLSI design of arithmetic circuits, residue number system, embedded architectures, DSPs, hardware/ software codesign and IT security. He has published more than 20 papers in international journals and conferences and he has been a principal researcher in three European research projects. Konstantinos Tatas received his degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece in 1999. He received his Ph.D. in the VLSI Design and Testing Center in the same University by June 2005. He has been employed as an RTL designer in INTRACOM SA, Greece between 2000 and 2003. His research interests include low-power VLSI design of DSP and multimedia systems, computer arithmetic, IP core design and design for reuse. Antonios Argyriou received the degree in Electrical and Computer engineering from the Democritous University of Thrace, Greece, in 2001, and the M.S. and Ph.D. degrees in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, in 2003 and 2005, respectively. His primary research interests include wireless networks, mobile computing and multimedia communications. He is a member of the IEEE and ACM. Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He is currently working as Ass. Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low power design, parallel architectures, embedded systems design, and VLSI signal processing. He has published more than 140 papers in international journals and conferences. He was leader and principal investigator in numerous research projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th and 6th IST). He has served as General Chair and Program Chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). He received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV). He is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. Antonios Thanailakis was born in Greece on August 5, 1940. He received B.Sc. degrees in physics and electrical engineering from the University of Thessaloniki, Greece, 1964 and 1968, respectively, and the Msc. and Ph.D. Degrees in electrical engineering and electronics from UMIST, Manchester, U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece, since 1977. He has been active in electronic device and VLSI system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientific and technical papers, as well as five textbooks. He was leader for carrying out research and development projects funded by Greece, EU, or other organizations on various topics of Microlectronics and VLSI Systems Design (e.g. NATO, ESPRIT, ACTS, STRIDE).     

流密码的现状和发展

密码技术，特别是加密技术是信息安全技术的核心。文中简要介绍了流密码的原理及种类，并对其设计准则及检验标准做了论述，接着概括了该领域的最新进展和成果，最后对其发展趋势进行了分析展望。