下一代网络终端管理系统体系结构及流程实现

为了实现下一代网络中大量异构终端网络和设备的远程集中监控和自助管理,满足用户终端网络与公众通信网络共同管理模式下的终端管理需求,提出下一代网络终端管理系统体系结构,详细分析了体系结构中的构成组件和相关功能. 该体系架构支持终端网络和设备的运行状态监控和业务保障,基于上下文管理和策略管理技术实现用户在异构终端环境下的自由通信,支持用户进行终端网络和设备的远程管理,并与公众通信网络运营支撑系统协作,实现用户终端网络和公众通信网络的统一管理. 通过业务使用和业务无缝接续场景说明了该终端管理系统的业务流程实现.     

基于ASL的模型驱动架构测试方法

针对模型驱动架构（MDA）下的软件开发方法中测试启动比较晚、难以发现隐藏在模型中的缺陷及UML模型描述缺乏精确语义等问题,提出了基于ASL的模型测试方法：从UML模型出发,将动作规约语言（ASL）运用于平台无关模型（PIM）上建立测试模型。给出了ASL语句在MDA过程中的工作原理、平台无关模型的建立过程、测试用例建立的步骤、测试执行的实施过程,最后结合实例,在UML图的基础上运用ASL对测试环境进行构建,并创建了系统的测试用例,对模型及业务逻辑进行了测试。实验结果表明,提出的基于ASL的模型测试方法既能利用模型驱动对复杂的测试用例进行简化和抽象,又能在软件生存期早期揭示软件的缺陷,防止缺陷随着软件开发过程的进行而被放大。     

Morphology and micromechanical behavior of binary blends comprising block copolymers having different architectures

Morphology and deformation behavior of binary blends comprising styrene/butadiene block copolymers (polystyrene content, Φ_PS∼0.70) having different molecular architectures were studied by means of transmission electron microscopy and tensile testing. In contrast to the binary diblock copolymer blends discussed in literature, the phase separation behavior of the blends investigated was found to be strongly affected by asymmetric molecular architecture. The blends showed macrophase separated grains, in which the structures resembled the microphase morphology of none of the blend components. Unlike the classical rubber-modified or particle-filled thermoplastics, neither debonding at the particle/matrix interface nor the particle cavitation was observed in these nanostructured blends. The microdeformation of the blends revealed plastic drawing of polystyrene lamellae or PS struts dispersed in rubbery matrix and orientation of the whole deformation structures along the strain direction.     

Supramolecular complexes: lamellar structure and crystalline transformation

Interfacial reaction of highly-branched polyethyleneimine (PEI) with octadecanoic acid (OA) was performed to prepare a series of supramolecular complexes (PEI(OA)_x). The complexes at solid state have typical lamellar structure, and the interlamellar distance can be modulated by the OA content. The long period values of the supramolecular complexes measured by SAXS were found to be dependent on the compositions, which are in good consistency with those measured by TEM. For example, the long period values from SAXS for PEI(OA)_0.76, PEI(OA)_1.03, and PEI(OA)_1.67 were 46.5, 62.7, and 56.2 Å, respectively. The corresponding data from TEM were 45.7, 60.7, and 56.6 Å, respectively. A model was proposed for the construction mode of the side alkyl chains (crystallization region) associated with PEI backbone (amorphous region), in which the side alkyl chains were arranged to be ‘end-to-end’ packing for the x=1 complex, while an ‘interdigitated structure’ of the side alkyl chains was deduced for the x>1 and x<1 complexes. Temperature variable FT-IR combination investigation of the scissoring band, rocking band, and stretching band of methylene (CH₂) and vibrational band of carbonyl group (CO) indicated that the crystalline form of the crystallization region in the lamellae can be transformed from orthorhombic to hexagonal with the temperature increasing, and vice versa.     

A new parallel lattice reduction algorithm for BKZ reduced bases

In order to implement the original BKZ algorithm in parallel,we describe it in terms of parallelism and give its parallel implementation scheme.Then we analyze the efficiency of algorithm’s parallel implementation and show that the speedup factor of BKZ algorithm in parallel is extremely low.Therefore we present a new parallel lattice reduction algorithm suitable for multiprocessor computer architecture.The new algorithm can obtain a BKZ reduced basis and the parallel speedup is effective.Also with the practical results,although the computational complexity increases compared with the original BKZ algorithm,we still indicate that the new algorithm performs well in parallel and the time cost in parallel is less.At the same time,we show that the length of the shortest vector is smaller.     

Map Reduce inspired loop mapping for coarse-grained reconfigurable architecture

Our work investigates how to map loops efficiently onto Coarse-Grained Reconfigurable Architecture （CGRA）. This paper examines the properties of CGRA and builds MapReduce inspired models for the loop parallelization problem. The proposed model has a more detailed performance metric and a more flexible unrolling scheme that can unroll different loop levels with different factors. A Geometric Programming based approach is proposed to resolve the optimization problem of loop parallelization problem. The proposed approach can find the optimal unrolling factor for each level loop, resulting in better parallelization of loops. Experimental results show that the proposed approach achieved up to 44% performance gain compared to the state-of-the-art loop mapping scheme.     

Towards evolvable Internet architecture-design constraints and models analysis

There is a general consensus about the success of Internet architecture in academia and industry. However, with the development of diversified application, the existing Internet architecture is facing more and more challenges in scalability, security, mobility and performance. A novel evolvable Internet architecture framework is proposed in this paper to meet the continuous changing application requirements. The basic idea of evolvability is relaxing the constraints that limit the development of the architecture while adhering to the core design principles of the Internet. Three important design constraints used to ensure the construction of the evolvable architecture, including the evolvability constraint, the economic adaptability constraint and the manageability constraint, are comprehensively described. We consider that the evolvable architecture can be developed from the network layer under these design constraints. What＇s more, we believe that the address system is the foundation of the Internet. Therefore, we propose a general address platform which provides a more open and efficient network environment for the research and development of the evolvable architecture.     

快速卷积算法的综述研究

卷积神经网络是深度学习算法应用最广泛的方向之一,目前卷积神经网络的应用不仅仅是停留在科技领域,已经扩展到医学、军事等领域,并且已在相关领域发挥着巨大的作用。卷积是卷积神经网络中最为核心的一部分,卷积运算占整个网络70%以上的时间,所以针对卷积运算的加速研究就显得十分重要。首先介绍近年来的卷积算法,并对其复杂度进行分析,总结了这些算法各自的优点和不足,最后对其理论研究和应用领域可能存在的突破进行了探讨和展望。     

面向物联网应用的SoC安全检查架构设计

物联网（IoT）应用的快速发展和软硬件开源化趋势使得IoT设备所面临的硬件安全威胁日益严峻,尤其是利用运行时条件触发的系统级攻击,很难通过传统测试方法进行检测和防御,需要提供运行时安全检查机制。分析IoT系统芯片面临的安全威胁,结合数据加密传输路径中的攻击、任务流和检查内容,设计4条功能完整性安全检查策略,搭建SoC安全策略检查架构并植入运行时触发硬件木马。仿真结果显示,运行时策略检查状态机可以检查出加密核、内存和UART接口的功能完整性问题,并通过发送错误中断信号进行反馈,证明了所设计的系统级安全策略检查架构的正确性与有效性。     

Carrier leakage and I/Q mismatch calibrated technique

The carrier leakage and I/Q mismatch calibrated technique based on the digital baseband for the direct conversion transmitter is described. The proposed technique only needs a calibration chain to detect mismatches, and then transmits them to the digital baseband, which completes the calibrated task. The proposed method is very simple in reducing die areas and power dissipation. Under TSMC 013μm CMOS technology simulation, the calibrated error of carrier leakage is less than 15％ and the error of I/Q mismatch is less than 65％．The measurement results indicate that I/Q amplitude mismatch is reflected at twice the input frequency. The calibrated chain gain range is 15dB with a 5dB step, and the bandwidth is 20MHz.