一种木马电路的实现与特征分析

由于硬件木马等恶意电路的隐蔽性,攻击者可以利用其窃取机密信息,破坏硬件电路,造成严重的经济损失与社会危害.本文基于典型的芯片设计流程与EDA工具,首先建立硬件木马的电路模型,然后尝试在一简单ADC芯片中,利用其电路的剩余空间,设计实现了一种计数器木马电路.该木马电路的规模大约占芯片总面积的5.6%,将受污染的电路与真实电路一起用标准CMOS工艺HJ0.25μm流片,然后采用旁路功耗分析技术进行深入分析.实验数据表明,在正常工作情况下,受污染和没受污染的芯片功耗并无明显差异,而当木马触发条件满足时,受污染的芯片却成功的实现了攻击.     

基于封装工艺识别翻新塑封集成电路

塑封集成电路在高可靠性领域应用越来越广泛,国内已有相当数量的塑封集成电路应用于国防领域。但是,目前大部分关键塑封集成电路依赖进口,采购渠道不是很通畅,市场中存在大量的翻新件。文章基于塑封集成电路封装工艺,简要介绍如何识别翻新塑封集成电路。     

基于不锈钢基板的厚膜电路制备技术

介绍了用丝网印刷法和低温烧结绝缘带转移法制备不锈钢绝缘基板的方法,比较分析了不同方法制得的不锈钢基板的绝缘性能,以及应用于Al2O3基板的浆料与绝缘带的相容性。还进行耐热冲击和自由落体试验,研究了不锈钢基板上介质覆盖层的结合强度。     

三维集成电路中的关键技术问题综述

评述了三维集成电路的发展状况及面临的关键技术难题。简要分析了三维集成电路的设计自动化算法,并与二维集成电路设计方法进行比较,指出了热驱动的物理设计和三维模块数据结构是制约三维集成电路设计自动化算法的关键因素。同时也详细介绍了三维集成电路中的关键互连技术——硅通孔(TSV)结构,给出了TSV的电路建模方法并对其发展趋势给予了展望。     

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.     

SiP组件中芯片失效机理与失效分析

由于分析手段与分析设备的限制,系统级封装（SiP）组件的芯片在失效分析的过程中带有一定的盲目性。结合故障树分析方法,以PM O S芯片失效为例,讨论了SiP组件常见的管芯失效机理：电应力失效、热应力失效、机械损伤和环境应力失效以及相应的失效现象;最后从设计和工艺角度提出了降低各种失效机理发生的改进措施。     

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Three-dimensional (3D) ICs have the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm,which takes use of quadratic uniformity modeling approach. In this model, cell distribution and thermal dissipation are integrated and formulated as a quadratic function through discrete cosine transformation (DCT) with wirelength optimization. Quadratic programming method is utilized to solve the unified quadratic objective function. We update the unified cell distribution and thermal dissipation with each step of the iterative placement process. Thermal distribution was considered enough during placement process even when a cell was moved. To save time, two fast methods to reflect thermal change were proposed for thermal distribution computation. The experimental results show our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wire length.     

铁氧体磁膜RF集成微电感等效电路分析

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.