The effect of forming gas anneal on the oxygen content in bonded copper layer

Using a combination of copper (Cu) thermocompression bonding and silicon wafer thinning, a face-to-face silicon bi-layer layer stack is fabricated. The oxygen content in the bonded Cu layer is analyzed using secondary ion mass spectrometry (SIMS). Copper-covered wafers that are exposed to the air for 12 h and 12 days prior to bonding exhibit 0.08 at.% and 2.96 at.% of oxygen, respectively. However, prebonding forming gas anneal at 150°C for 15 min on 12-day-old Cu wafers successfully reduces the oxygen content in the bonded Cu layer to 0.52 at.%.     

《射频通信电路》教材的编写思路和内容特点

射频电路已成为移动通信系统的设计瓶颈,现在射频集成电路设计师也已成为热门职业之一。我们为本科生提供了一本讲述射频通信电路的基础教科书。本文介绍了该书的三个特点：一是在主要讲述射频通信电路设计的同时,也提供了其它相关领域的基础背景知识;二是对收发机各模块的性能指标,原理和设计方法进行了系统地论述;三是将系统设计,模块设计和模块应用紧密结合在一起。     

不同状态的Si-Al丝对键合点根部损伤的影响

键合点根部损伤是Al丝超声键合工艺中最常见的问题,严重的根部损伤不仅使焊点的键合强度降低,甚至会使键合点失效。通过优化键合机器的工艺参数、分析键合丝的组分和采取不同的退火条件,研究Al丝超声键合中,键合点根部损伤的程度,为键合丝的选用和提高Al丝超声键合强度提供依据。     

Thermal Testing of Analogue Integrated Circuits: A Case Study

This paper discusses the use of temperature as a test observable for analogue circuits, presenting a generic configuration for analogue circuit thermal testing. As a case study, static temperature analysis is performed over a two-stage operational amplifier in view of extracting temperature waveforms at different locations on the circuit under test, both under fault-free conditions as well as in the presence of bridging faults. Exhaustive thermal analysis of all the likely bridging faults is presented, establishing the detectability ratio of this fault set using temperature under different sensing scenarios.     

Irradiation effects on passivated NMOS-transistors caused by electron beam testing

Up to now for electron beam testing of passivated integrated circuits a high energetic electron beam is used, which shorts the passivation layer and enables the measurements of the voltage signals at the covered conductor tracks. Experiments at passivated NMOS-transistors show, however, that though using the lowest primary electron energy possible to build up the necessary conductive channel even low electron irradiation doses give rise to significant changes of the device characteristics. Therefore this way has to be excluded for electron beam testing of passivated integrated MOS-circuits.     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

典型器件和电路不同剂量率的辐射效应

对几十种不同类型的典型星用器件和电路在不同剂量率辐照下的响应规律及退火特性进行了研究。对双极器件和电路及JFET输入运算放大器电路产生低剂量率损伤增强效应的机理进行了分析。结果显示,器件类型不同,失效模式也相异。其典型的失效模式表现为4种:a)仅有低剂量率辐照损伤增强效应;b)既有低剂量率辐照损伤增强效应,又有时间相关效应;c)仅有时间相关效应;d)无不同剂量率辐照损伤间的差异。     

A practical assessment of current plastic encapsulated microelectronic devices

The use of plastic encapsulated devices (PEDs) for a variety of market sectors has been the subject of much discussion over the past two decades. The advantages of lower cost together with the inherent mechanical ruggedness of these non-cavity packages have been weighed against the concerns over quality and reliability and, in particular, electrical operation at extremes of temperature. This paper presents the results of some practical work undertaken on a modern LSI device in a plastic leaded chip carrier package. It then discusses British Telecom's experience with PEDs to date and concludes with some general considerations on the quality assurance requirements a purchaser may place on vendors of such devices.     

Integrated solutions for GSM terminals

GSM is the most successful operating digital cellular communications system. Over the past few years the cost of handsets has plummeted while performance and attractiveness have improved significantly. This is due to the advances in IC technology, integration and new architectural approaches. This paper reviews the GSM standard and considers those aspects most significant for terminal design. It describes the different approaches and trade-offs involved in the development of a modern handset implementation and their realization as a commercial chipset. The different functional blocks of a terminal are reviewed, and the design choices, process technologies and partitioning strategies most applicable for each stage are compared. Finally, a brief discussion of some future possibilities and opportunities for further development is presented.     

Improved transmission line model for high-frequency modelling of through silicon vias

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.