Integration of GaN analog building blocks on p-GaN wafers for GaN Ics

We demonstrate the key module of comparators in GaN ICs,based on resistor-transistor logic(RTL)on E-mode wafers in this work.The fundamental inverters in the comparator consist of a p-GaN gate HEMT and a 2DEG resistor as the load.The function of the RTL comparators is finally verified by a undervoltage lockout(UVLO)circuit.The compatibility of this cir-cuit with the current p-GaN technology paves the way for integrating logic ICs together with the power devices.     

集成电路互连线电迁移建模综述

简要介绍了集成电路互连线建模发展的历史。回顾了曾广泛使用的一维电迁移引起的回流模型。基于原子通量散度的概念,电迁移建模可以分为两种方法。一种是常用的扩散路径法,该方法能够解释传统的铝片上金属互连的许多重要电迁移现象。然而,随着芯片尺寸越来越小,工业界为了追求更好的性能,转向了使用铜/低k组合作为互连材料,同时引进了三维集成电路技术。顺应这种趋势,第二种驱动力电迁移建模方法发展了起来,该方法有助于人们理解窄互连工艺中的许多现象。有限元模拟也越来越多地用于驱动力分析法。     

寄存器传输级测试用例生成算法

基于控制流图／数据流图层次模型,以分支覆盖、位功能覆盖以及语句可观测覆盖为目标,给出一个高层次测试用例生成算法,并最终实现一种可行的RTL级测试生成算法．实验结果表明,在较少的测试生成时间下,该算法可生成相对短的测试序列,得到与其他方法相当或略差的测试效果．此外,该算法因采用了测试用例技术而具有良好的灵活性．     

On-Line Fault Resilience Through Gracefully Degradable ASICs

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic reconfigurations are performed dynamically through operation rescheduling and hardware rebinding. Instead of a complete shuffling, the proposed scheme perturbs the original schedule and binding in a systematic fashion. This regularity of the scheme allows well-structured design planning for the controller and the datapath. The underlying microarchitecture supporting such reconfiguration schemes is briefly outlined. Experimental evidence indicates negligible performance and small hardware overheads.     

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs

A methodology is proposed to characterize through silicon via (TSV) induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using the 3D transmission line matrix (TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type, placement of substrate contacts, signal slew rate and voltage swing. The effect of differential TSV signaling is also investigated. Design guidelines are developed based on these results.     

Equivalent Circuit Analysis of an RF Integrated Inductor with Ferrite Thin-Film

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

PDP驱动芯片中高压LDMOS建模

建立了PDP驱动芯片用高压LDMOS的SPICE子电路模型,该模型集成了LDMoS固有特性:准饱和特性、电压控漂移区电阻、自热效应、密勒电容等.与其他物理模型和子电路模型比较,该模型不但能提供准确的模拟结果,而且建模简单快捷,另外该模型可较容易地嵌入SPICE模拟软件中.模型的实际应用结果显示:模拟与实测结果误差在5%以内.     

LED显示屏驱动芯片的种类及应用

主要介绍LED显示屏驱动芯片种类及关键参数，对市场上主流厂商的芯片进行了性能对比，并对芯片的应用提出了一些建议。     

Statistical Design of a 10 bit Current Division Network

The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.