边界元法在数模混合集成电路衬底耦合参数提取中的应用

把边界元方法运用到数模混合集成电路衬底耦合电阻参数的提取.求出了满足衬底边界条件的格林函数,而不是采用三维自由空间的格林函数,从而使需离散的边界仅仅是衬底表面的端口区.在计算阻抗元素时,利用基于快速富立叶变换(FFT)的离散余弦变换(DCT)使计算速度大大提高.和有限差分法相比,精度差不多而计算速度提高一个数量级以上.计算精度比Wemple采用解析方法计算有很大的提高     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

一种混合晶向结构硅片研究

为15V-40V电压集成电路和MEMS传感器潜在应用,研发了两种5μm厚的混合晶向结构硅片。这种结构采用以键合SOI硅片和非选择性外延为主的方法实现。这种结构在国内首次被报道。这种结构埋氧层厚度为220nm,通过“Sirtl”缺陷显示液发现以（100）晶向为衬底的混合晶向结构硅片质量好于以（110）为衬底的混合晶向硅片。     

Timing-driven via placement heuristics for three-dimensional ICs

The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

Reliability simulation for analog ICs: Goals,solutions, and challenges

The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

塑封器件的外部目检方法与判据研究

目前,塑封器件由于其在尺寸、重量、成本、可用性和性能,以及工艺和设计方面的先进性,使得其在高可靠性领域中的应用越来越广泛,国内已有相当数量的塑封器件应用于国防领域。但是,其外部目检试验项目所依据的方法与判据仍然沿用气密性封装器件外部目检的方法与判据,已经不能满足日益增多的塑封器件的外部目检筛选要求。结合GJB 548B-2005的方法 2009.1外部目检要求,开展塑封器件外部目检试验方法与判据的研究。     

基于常规CMOS工艺的电子镇流器芯片设计

分析当前主流电子镇流器控制芯片的优缺点,提出了一种适用于功率在20W以下节能灯控制芯片的设计方案。采用常规的CMOS铝栅工艺。整个控制芯片由主芯片和高压管驱动两块芯片组成,两管间通过自举电容耦合。自举电容起的作用：（1）隔离高压（2）传输高压功率管的控制信号。此设计方案的难点是设计出符合上述设计要求的高压管驱动芯片。此款芯片采用6μm CMOS铝栅工艺模型,经仿真验证,现已通过MPW流片成功。测试各项指标都达到设计要求。     

Epitaxial spinel growth for integrated circuits

This is a report on our investigation of the epitaxial growth of Si-on-spinel-on-Si double-heterostructure integrated circuit material. The spinel epitaxial layers were grown on the Si substrate with an open-tube Al-HCl-MgCl₂-CO₂H₂ VPE system. High electron Hall-mobility and low defect density in the active Si layers were achieved with optimum growth conditions for spinel and silicon. Bipolar transistors, MOS devices and high-voltage bipolar ICs were fabricated in the active Si layers on epitaxially grown spinel.