基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

借助普通运放组成电路实现对交流信号的采集

用两片集成电路LF347组成带参考端的交流信号采集电路,具有整流、滤波和比例放大的功能,实现了对中低频信号的采集。理论分析和实验测试均得出一致结论:当交流输入端信号和参考端信号同相则输出正值,二者反相则输出负值。该电路输出为标准的CMOS电平,便于A/D采集,算法简单。在应用中该电路调节方便,具有和相同功能的集成电路LZX1一致的线性度和精度,性能价格比高。     

A Low-Power Block-Matching Cell for Video Compression

This paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 mtechnology and the measured energyconsumption is 1.2 nJ per block match usingan pixel matrix. Simulations ofthe same cell in 0.35 m and 0.25 mCMOS technology are presented, showing thescalability of the approach.     

基于DPA425的开关电源的设计与研制

DPA-Switch是新一代的高集成度、高压DC-DC转换芯片,其电路简单,不仅具有分立元器件开关电源极为灵活的优势,而且可以提高DC-DC变换器的可靠性,并能降低成本。本文介绍了该系列集成控制器的原理及其在DC-DC反激变换器中的应用,并给出了设计实例。     

创新型超薄IC封装技术

圆片薄型化工艺技术的改进,以及对小型化、便携式产品的强烈的市场需求,共同推动了封装技术的创新。文中主要论述了与超薄型集成电路封装技术相关的薄型硅集成电路应用、超薄型圆片的制造、薄型化切割技术、同平面互连技术、倒装片装配及其可靠性问题。     

VDSM ULSI布局布线优化设计研究

本文基于超大规模集成电路特征尺寸进入超深亚微米层次下的金属互连(interconnects)特性,研究并提出了布局布线优化步骤:局部布局和搜索提炼、轨道分配和搜索修补.并结合synopsys公司的超深亚微米布局布线系统APOLLO-Ⅱ有效地解决了金属互连的拥挤和时序问题.     

Timing-driven via placement heuristics for three-dimensional ICs

The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion.     

Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs

In this paper, we investigate the co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. The architecture is a 16 core, ×86 multicore die stacked with a second die hosting an L2 SRAM cache. First, a multicore ×86 compatible cycle-level microarchitecture simulator was constructed and integrated with physical power models. The simulator executes benchmark programs to create power traces that drive thermal analysis. Second, the thermal characteristics under liquid cooling were investigated using a compact thermal model. Four alternative packaging organizations were studied and compared. The greatest overall temperature reduction under a given pumping power is achieved, with two tiers and two pin fin enhanced microgaps, with the high power dissipation tier on the top. Third, an optimization of the pin fin parameters including the diameter, height, and longitudinal and transversal spacing was performed. This optimization is shown to achieve significant improvement in energy/instruction, and significant reductions in leakage power.     

A prediction technique for single-event effects on complex integrated circuits

The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%.     

集成电路的发展和组装工艺的考虑

介绍了集成电路的发展对组装工艺带来的影响，为了迎接这一挑战，在电子组装工艺方面应该考虑的问题。