Stress analysis of 3-dimensional IC package as function of structural design parameters

Solid Liquid Inter-Diffusion (SLID) is a technology that has recently been utilized to fabricate 3D ICs. Since application of this technology is in its infancy stages, manufacturability and reliability of these bonds are still under heavy investigations. This study presents an elastic-plastic finite element and analytical analyses that were implemented to evaluate effect of package design parameters on thermo-mechanical reliability of the SLID bonds and copper interconnects. A numerical experiment is designed in which several design parameters; die thickness, bond size, underfill stiffness and substrate thickness, are varied in 3 levels. Stress in SLID bonds and in copper interconnects were evaluated using the 3-dimensional finite element analysis as well as an analytical approach. The results show that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Results of the analytical approach confirm the finite element analysis. It is shown that effect of interconnect size and pitch is very small compared to die thickness. In average increasing die thickness increases both shear and peeling stresses at the interfaces and copper interconnects.     

塑封集成电路离层对可靠性的影响及解决方法

塑封集成电路因其是非气密性封装,封装材料热膨胀系数的不同以及被粘接材料表面能低,是造成塑封电路离层或开裂的内部原因。通过选择特殊的封装材料（特别是框架材料）和工艺可以解决离层或开裂问题,大大提高塑封集成电路的稳定性和可靠性。水汽是造成塑封集成电路离层或开裂的外部原因,可以通过驱除和防潮措施来解决。要提升塑封集成电路可靠性,必须从技术和工艺上解决塑封电路离层或开裂问题。我们在这方面做了有益的尝试,取得了良好的效果,为拓展塑封集成电路的应用领域创造了条件。     

Novel lateral IGBT with n-region controlled anode on SOI substrate

A new lateral insulated-gate bipolar transistor (LIGBT) structure on SOI substrate, called an n-region controlled anode LIGBT (NCA-LIGBT), is proposed and discussed. The n-region controlled anode concept results in fast switch speeds, efficient area usage and effective suppression NDR in forward I-V characteristics. Simulation results of the key parameters (n-region doping concentration, length, thickness and p-base doping concentration) show that the NCA-LIGBT has a good tradeoff between turn-off time and on-state voltage drop. The proposed LIGBT is a novel device for power ICs such as PDP scan driver ICs.     

从一本外文教材中得到的感受

本文简要介绍了T．H．Lee“The Desing of CMOS Radio Frequency Integrated Circuits”的内容，并由此谈谈高频（或非线性）电子线路课程改革的一点看法。     

LOMACH — a MOS circuit mask checking logic simulator

Logic simulators were originally developed for logic diagram verification. Their use for mask verification is a complex task of logic diagram recognition based on the information gained from masks to be made. The simulator LOMACH is based on the idea that logic states do not propagate through the nodes of a logic diagram but rather through diffusion regions defined directly by the masks. This paper provides postulates governing the logic state wave propagation, and suggests an internal database and algorithms for checking topological correctness and logic function simulation.     

Plastic‐film displays with NanoBlock IC drivers integrated by a fluidic self‐assembly process

Abstract— High‐performance compact plastic displays have been built by integrating high‐quality crystalline‐Si NanoBlock IC drivers into plastic films using a fluidic self‐assembly (FSA) process. Plastic‐film‐based liquid‐crystal displays, only 500 μm thick, were integrated into smartcards using NanoBlock IC voltage drivers. In an additional demonstration, polymer‐LED displays were constructed using NanoBlock IC current drivers. FSA technology provides a cost‐effective means of packaging integrated circuits within plastic film, enabling high‐performance backplanes that can be combined with a variety of display media.     

多功能新型Apple-Ⅱ逻辑功能测试卡

本文讨论了一种简单、有效,在Apple-Ⅱ微机系统上实现测试74/54系列ICs的逻辑功能,提供其逻辑接线图,搜索出功能正常但型号不明之芯片的型号,测试同一芯片上各独立逻辑功能组件的逻辑功能的测试装置。系统的工作原理基于存贮响应法:即向被测件提供测试图形并取回相应的响应图形与机内存贮的“正确”响应相比较。文中给出了一种器件的测试数据。所讨论的思想方法适用于对系统功能的再扩展。     

Evolution of a CMOS Based Lateral High Voltage Technology Concept

This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.V_GS=max.V_DS=3.3V, max.V_GS=max.V_DS=5.5 V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35 μm CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.