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21.
The parallelism of loop nests with non-uniform dependences is difficult to extract and ineffectively explored by the existing parallelization schemes. In this paper, we propose new efficient techniques in extracting parallelism of loop nests with non-uniform dependences using their irregularity. By this way, current highly parallel multiprocessor systems such as multithreaded and clustering multiprocessor systems can be fully utilized. These four mechanisms are (a) parallelization part splitting, (b) partial parallelization decomposition, (c) irregular loop interchange and (d) growing pattern detection. They explore parallelisms of special parallel patterns for nested loops with non-uniform dependences. The loop transformations used in uniform loops are also applied in non-uniform dependence loops after legality tests. We apply the results of classical convex theory and detect special parallel patterns of dependence vectors. We also proposed an algorithm that combines above mechanisms to enhance parallelism. We demonstrate that our technique gives much better speedup and extracts more parallelism than the existing techniques. Thus, we are encouraged by these apparent enhancements to pursue further development. 相似文献
22.
The problem of packing circles into a domain of prescribed topology is considered. The circles need not have equal radii. The Collins-Stephenson algorithm computes such a circle packing. This algorithm is parallelized in two different ways and its performance is reported for a triangular, planar domain test case. The implementation uses the highly parallel graphics processing unit (GPU) on commodity hardware. The speedups so achieved are discussed based on a number of experiments. 相似文献
23.
Effective tool wear monitoring (TWM) is essential for accurately assessing the degree of tool wear and for timely preventive maintenance. Existing data-driven monitoring methods mainly rely on complex feature engineering, which reduces the monitoring efficiency. This paper proposes a novel TWM model based on a parallel residual and stacked bidirectional long short-term memory (PRes–SBiLSTM) network. First, a parallel residual network (PResNet) is used to extract the multi-scale local features of sensor signals adaptively. Subsequently, a stacked bidirectional long short-term memory (SBiLSTM) network is used to obtain the time-series features related to the tool wear characteristics. Finally, the predicted tool wear value is outputted through a fully connected network. A smoothing correction method is applied to improve the prediction accuracy. The proposed model is experimentally verified to have a high prediction accuracy without sacrificing its generalization ability. A TWM system framework based on the PRes–SBiLSTM network is proposed, which has a certain reference value for TWM in actual industrial environments. 相似文献
24.
This paper presents the analysis of a parallel formulation of depth-first search. At the heart of this parallel formulation is a dynamic work-distribution scheme that divides the work between different processors. The effectiveness of the parallel formulation is strongly influenced by the work-distribution scheme and the target architecture. We introduce the concept of isoefficiency function to characterize the effectiveness of different architectures and work-distribution schemes. Many researchers considered the ring architecture to be quite suitable for parallel depth-first search. Our analytical and experimental results show that hypercube and shared-memory architectures are significantly better. The analysis of previously known work-distribution schemes motivated the design of substantially improved schemes for ring and shared-memory architectures. In particular, we present a work-distribution algorithm that guarantees close to optimal performance on a shared-memory/-network-with-message-combining architecture (e.g. RP3). Much of the analysis presented in this paper is applicable to other parallel algorithms in which work is dynamically shared between different processors (e.g., parallel divide-and-conquer algorithms). The concept of isoefficiency is useful in characterizing the scalability of a variety of parallel algorithms.This work was supported by Army Research Office Grant No. DAAG29-84-K-0060 to the Artificial Intelligence Laboratory, and Office of Naval Research Grant N00014-86-K-0763 to the Computer Science Department at the University of Texas at Austin. 相似文献
25.
针对非对称并联机构在某些方面有着特殊的应用但研究较少的现状,对一种非对称6-PSS并联机构工作空间和灵活度进行了研究,得到了其工作空间和灵活度随结构参数和姿态要求的变化规律,得出此机构可以应用在y轴方向工作空间要求大,而绕x轴转角要求不高的场合。为进一步扩大并联机构的实际应用提供了依据。 相似文献
26.
运动学标定就是对实际几何参数的估计过程,通过标定来减少动平台的位姿误差。本文对并联机构的标定技术进行了介绍,并对一种四自由度并联机构的标定过程以两种标定方法进行了说明,给出了仿真结果。 相似文献
27.
气动逻辑元件在多气缸顺序动作气压控制回路中的应用 总被引:1,自引:0,他引:1
朱光力 《组合机床与自动化加工技术》2003,(8):60-61
以三坐标气动机械手为例子来说明气动逻辑元件在多气缸顺序动作的气压控制回路中的应用,从而使得气动控制回路的设计变得简单明了。 相似文献
28.
一种新的变轴数控机床标定方法 总被引:1,自引:0,他引:1
本文论述了国内外并联数控机床所采用的标定方法,选择了序列法进行了标定试验。但在实际标定过程中,出现了部分数据误差较大的问题,本文针对所面临的问题,提出了数值逼近法,并应用到实际机床的标定中,获得了机床的相关参数。之后,通过数学模型的计算值和实际测量值对比,验证了数据的可靠性,从而验证了方法的可行性和正确性。 相似文献
29.
This contribution concerns variance analysis of linear multi-input single-output models when the inputs are temporally white but where different inputs may be correlated. An expression is provided for the variance of a linearly parametrized estimate of the frequency response function from one block, i.e. from one input to the output. In particular, this expression reveals that the variance increases in one block when the number of estimated parameters in another block is increased, but levels off when the number of parameters in the other block reaches the number of parameters in the block in question. It also quantifies exactly how correlation between inputs affects the resulting accuracy and a graphical representation is provided for this purpose. The results are applicable to parallel MISO Hammerstein models when the nonlinearities are known and generalize an existing variance expression for this type of model. 相似文献
30.
We have designed Particle-in-Cell algorithms for emerging architectures. These algorithms share a common approach, using fine-grained tiles, but different implementations depending on the architecture. On the GPU, there were two different implementations, one with atomic operations and one with no data collisions, using CUDA C and Fortran. Speedups up to about 50 compared to a single core of the Intel i7 processor have been achieved. There was also an implementation for traditional multi-core processors using OpenMP which achieved high parallel efficiency. We believe that this approach should work for other emerging designs such as Intel Phi coprocessor from the Intel MIC architecture. 相似文献