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71.
本文介绍了一种自发电鼠标装置,该作品采用压电陶瓷、硅胶等新型材料进行设计,在原始无线鼠标底部及两侧安装3个串联的压电陶瓷,并放置重力小球.利用等效替代法通过无线鼠标内置重力感应小球运动撞击按压压电陶瓷产生电能,并通过升压稳压电路产生平稳电流,存储在锂电池中代替干电池支持鼠标工作.自发电理念缓解大量使用干电池造成环境二次污染的问题,有利于实现社会可持续发展.此外,引用基于信号强度的射频识别技术开发可在空间三维移动的鼠标,并能记录其三维移动轨迹.通过MEMS加速度传感器和触控模块,感知鼠标的移动动作,实现鼠标的空间三维移动. 相似文献
72.
随着通信行业节能减排的进一步推进,合同能源管理作为一种全新的节能模式引起关注,其实质就是以节省的电费来支付节能改造的投资,但在实际应用中会面临技术选择、方案选择以及合同付款等问题。文中针对上述问题提供一种比较详细的解决方案。 相似文献
73.
电力网线损是在输电过程中所产生的功率损耗,这种不必要的损耗应当加以控制,以达到节约能源的目的。文中主要对如何有效的降低线损,以及加强线损工作的管理进行了研究和探讨,以达到电力网运行的最佳状态。 相似文献
74.
Duo Li Author Vitae Author Vitae 《Integration, the VLSI Journal》2010,43(2):167-175
One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches. 相似文献
75.
基于微型光机电系统扫描镜技术的激光散斑抑制方法 总被引:1,自引:0,他引:1
激光固有的时间和空间相干性,造成的散斑现象成为实现激光显示技术的瓶颈。针对激光显示的消散斑问题,提出了一种基于微型光机电系统(MOEMS)扫描镜技术的散斑抑制方法,并设计了一种简单的二维扫描镜结构,为开发非运动式、小体积、低功耗、高速低成本电调制的MOEMS,实现对激光散斑的抑制,标准化消相干器件的工艺的开发和规模化生产技术提供了参考。 相似文献
76.
Electrochemistry: Development and Simulation of Sulfur‐doped Graphene Supported Platinum with Exemplary Stability and Activity Towards Oxygen Reduction (Adv. Funct. Mater. 27/2014)
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77.
A new feature selection method is proposed for high-dimensional data clustering on the basis of data field. With the potential entropy to evaluate the importance of feature subsets, features are filtered by removing unimportant features or noises from the original datasets. Experiments show that the proposed method can sharply reduce the number of dimensions and effectively improve the clustering performance on WDBC dataset. 相似文献
78.
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Ozgur Sinanoglu 《Journal of Electronic Testing》2008,24(4):335-351
Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent
test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power
thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that
can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification
technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce
the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact
of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully
modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power.
The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification,
which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
Ozgur SinanogluEmail: |
Ozgur Sinanoglu received a B.S. degree in Computer Engineering, and another B.S. degree in Electrical and Electronics Engineering, both from Bogazici University in Turkey in 1999. He earned his M.S. and Ph.D. degrees in the Computer Science and Engineering department of University of California, San Diego, in 2001 and 2004, respectively. Between 2004 and 2006, he worked as a senior design for testability engineer in Qualcomm, located in San Diego, California. Since Fall 2006, he has been a faculty member in the Mathematics and Computer Science Department of Kuwait University. His research field is the design for testability of VLSI circuits. 相似文献
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