声表面波可程序抽头延迟线研究

报道声表面波可程序抽头延迟线的研制情况。对该器件的总体结构，电路原理框图、声表面波可程序抽头延迟线结构作了一个扼要的概念。同时分别报道了我所研制的各类声表面波可程序抽头延迟线器件性能指标及相应的图片说明，最后对该器件仍存在的一些问题作了探讨。     

离散效应存在时孤子脉冲的增强压缩

在群速度不匹配的条件下，提出一种提高孤子脉冲压缩效应的新方法．研究表明，若使信号脉冲与泵浦脉冲存在一适当的初始延时，则不但可以提高离散效应单独存在时信号脉冲的压缩比，而且可以提高孤子脉冲的压缩质量．     

八里庄钢筋混凝土桥控爆拆除

文中介绍在周期建筑，电力、电信等设计密集的环境中，爆破一座结构坚固的大型钢筋混凝土桥梁和桥台浆砌块石的爆破参数设计，局部部位技术处理措施以及孔内孔外延时相结合的非电起爆网路。     

Identification of delayed system using instrumental variable method

System identification uses system inputs and outputs to raise mathematical models.Various techniques of system identification exist that offer a nominal model and an uncertainty bound.Many practical systems such as thermal processes & chemical processes have inbuilt time delay.If the time delay used in the system model for controller design does not concur with the actual process time delay,a closed-loop system may be unstable or demonstrate unacceptable transient response characteristics so here the time delay is assumed to be time-invariant. This paper proposes on-line identification of delayed complex/uncertain systems using instrumental variable(Ⅳ) method.Parametric uncertainty has been considered which may be represented by variations of certain system parameters over some possible range.This method allows consistent estimation when the system parameters are associated with the noise terms,as the IV methods(IVM’s)usually make no assumption on the noise correlation configuration.The faster convergence of the parameters including noise terms has been proved in this paper.Iterative prefiltering(IP)method has also been used for the identification of the delayed uncertain system and the graphical results given in this paper demonstrate that the convergence results are inferior to the instrumental variable method.     

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.     

基于IPv6组播的M-FHM IPv6切换技术

由于快速分层切换技术FHMIPv6将FMIPv6和HMIPv6切换技术结合起来,因此,在层次移动管理模型中部署快速切换时具有两种技术所具有的优点,可使切换延时进一步减少。文中通过对FHMIPv6的研究发现,其切换过程中DAD重复地址检测过程严重影响了切换性能,因此提出了基于IPv6组播的M-FHMIPv6切换技术。理论分析证明,M-FHMIPv6能有效减少DAD检测过程和各种信息交互的延迟。通过NS2实验仿真进一步说明:改进的M-FHMIPv6方案能减少切换延迟,平滑切换过程。     

数字磁通门传感器的自动相位对准

三轴数字磁通门传感器信号处理电路的延时(相位延迟)及各轴延时不一致,影响数字滤波器的输出性能。提出了基于加权最小二乘法的互功率谱相位法计算延时的方法,针对该数字滤波器的特性,选择传感器的不同谐波信号对比分析相位延迟计算的精度,并设计了传感器的自动相位对准方法。实验结果表明:该计算方法精确有效,自动相位对准使滤波器输出性能提高25.89%。     

自适应回声对消的初期迭代统计学模型及改进算法

为减少滤波器长度,提出自适应滤波算法初期迭代统计学模型及改进的回声消除算法。提出的统计学模型分析了自适应算法迭代初期滤波器各系数的均值和方差。基于该模型提出的改进算法,先检测回声路径峰值,进而确定回声路径延时,然后以延时为中心,用一个短的滤波器辨识原回声路径活跃系数部分。用实际回声路径进行仿真,理论和实验结果均表明,新算法在迭代的前75～100步已可准确检测回声路径峰值并确定延时;而减少滤波器长度,可大幅提高自适应算法收敛速度并降低算法计算复杂度。