智慧城市网络安全问题探讨

智慧城市是以物联网、互联网等通信网络为基础,通过物联网、互联网、智能使城市各功能模块协同运行的新型城市发展模式。它的特点是高度集成的智能技术,智能产业的高端发展和高效便捷的智能服务。然而,随着一切都变得更加互联和依赖技术,城市变得更加“智能”,这意味着它们不可避免地拥有更多的技术基础设施和数据,这意味着它们更容易受到新的威胁,随之而来的是更多的网络安全隐患。文章探讨了智慧城市带来的网络安全问题,并给出了相应的解决方案,使得智慧城市的建设更加安全,能更好的改善市民的生活,使得城市治理更加有效。     

Solar control with thermotropic layers

Innovative means to control the light and energy flux according to demand are desirable for transparent façades and façade elements. One possibility to achieve this is presented by switchable layers that change their optical properties, either actively or passively, according to different control parameters. In addition to inorganic coatings on glass, there are several organic thermotropic systems that can be integrated into façade glazing. Above a certain temperature, thermotropic layers change from a clear to a translucent, light-diffusing state, thus switching from a highly transmitting to a diffusely reflecting state. We shall describe the basic principles of these systems and present an overview of some of the existing prototype systems. Installation options will be discussed and the results of an application in a retrofitted building presented.     

信息技术应用于智慧桥梁的研究与展望

通过对数据、信息、知识和智慧的内涵阐述,以桥梁全寿命周期的数据、信息、知识和智慧为基础,研究探索了新兴信息技术在智慧桥梁各阶段的应用方式和价值,并介绍了上海同豪土木工程咨询有限公司在信息技术应用于智慧桥梁领域的研发实践和规划。     

基于校园网数控机床实践教学的研究

这里提出基于校园网，加强信息共享，在数控机床实践教学中，引入虚拟数控机床，进一步提高和完善实习教学，而且作为节能降耗的另一种新手段已成为可能。利用虚拟现实技术，提高学生的学习兴趣，扩大学生的视野，可获得良好的教学效果。     

高校室外公共活动空间的思考与探索——以华中师范大学为例

当今高校既是培养高素质人才的基地，也是社会文化的源泉。室外公共活动空间是校园环境的重要组成部分，创造良好校园环境，成为教育事业发展的前提和基础。该文以对华中师范大学室外公共空间的研究与分析为例，分析高等学校室外公共活动空间存在的问题，寻求适合高校室外公共活动空间的设计方法。     

基站主设备智能节电技术探讨

对2种智能节电技术的基本原理进行了分析,根据试验数据探讨了智能节电技术的节电效果和影响因素,并给出了相应的应用建议。     

高校校园网络病毒及防范措施

分析了网络病毒对校园网的危害以及病毒在网络中的各种传播方式,提出了校园网病毒的防治应从管理措施上着手,并综合防火墙技术、病毒防治软件、软件更新、数据备份等多种技术措施对网络病毒进行防治。     

Multistage distribution network expansion planning under smart grids environment

This paper presents a novel model for multistage smart distribution network expansion planning (MSDNEP) in the presence of vehicle to grid (V2G) and fault passage indicator (FPI) in a multi-objective optimization framework. Distribution networks should be expanded in order to serve load growth in the best manner possible. The two objectives considered are: minimization of total cost during the planning horizon and maximization of reliability index. The proposed model determines the sitting and sizing of parking lot as well as conventional alternatives for expansion, such as, optimal size, location and time in which the new lines must be added, replaced or removed. Moreover, the impacts of using FPIs in a distribution network on reliability and the investment cost are in the scope of this study. Due to its good handling of mixed integer nonlinear problem, a non-dominated sorting genetic algorithm (NSGA-II) is utilized for optimization such a complex problem. The effectiveness of the proposed model is demonstrated by applying to a distribution test system and results show a significant improvement in the area of distribution network planning.     

A network scheme for process bus in smart substations without using external synchronization

The development of smart substations plays a crucial role in the development of smart grid. The major difference between a smart substation and an existing conventional substation lies in the process bus. Based on a thorough study over the network schemes of sampled values for process bus in smart substations, this paper summarizes and analyses major characteristics of existing network schemes. In order to overcome shortcomings of existing network schemes in time synchronization, the paper proposes a novel network scheme for process bus in smart substations without using external synchronizing clock. Compared to conventional network schemes, the proposed scheme does not need an external global synchronizing clock, thus can significantly improve the reliability of the process bus network. As a major research output of the key technological project, this work has been successfully applied to the 110 kV Shenxiang Substation in Suzhou, China.     

13-bit GaAs serial-to-parallel converter with compact layout for core-chip applications

Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency.