GSM900／GSM1800双频网技术解决方案初步探讨

介绍了GSM1800的特点,并从网络设计方面对双频网的组网方式、覆盖方式、话务控制、切换算法等技术解决方案进行了初步探讨。     

一类切换系统切换序列的优化设计

针对切换系统中子系统最优且稳定与系统总体最优与稳定之间的关系问题,研究了一类由任意多子系统组成的切换总次数、切换次序、切换时刻均为系统变量的切换系统,指出设计最优的切换序列是切换系统最优控制的关键.在切换总次数和切换次序没有事先确定的情况下,给出了包括切换总次数、切换次序、切换时刻3组变量的代价函数,然后利用遗传算法求...     

LEFP 成型及侵彻过程的数值模拟

为反映线性爆炸成型侵彻体（liner explosive formation penetration,LEFP）成型及侵彻过程中各参数的变化规律,合理设计LEFP装药结构参数,利用LS-DYNA 3D有限元动力分析软件,采用任意拉格朗日-欧拉（ALE）算法,建立包括炸药、药型罩、壳体、空气、靶板在内的三维数值模型,在分析线性爆炸成型侵彻体成型过程的基础上,通过数值模拟和实验进一步分析了LEFP对45#有限钢靶板的侵彻效应。结果表明,该模拟方法正确,能为LEFP的设计提供参考。     

智能天线技术及应用研究评述

智能天线是提高无线传输性能的一项关键技术,是无线通信领域持续的研究热点之一,其中部分研究成果已经在无线通信、雷达、电子对抗等广泛的领域获得了成功的应用,并且未来无线系统设计中会越来越多的采用智能天线技术.为此,文章首先简要回顾了有关智能天线技术的发展历史,介绍了其中主要的阵列处理算法原理,给出了基于软件无线电和FPGA/DSP等可重配置软硬件系统设计参考方案,通过一些设计实例分析了应用中的实际问题和解决途径,最后提出了有关这一技术领域未来发展的展望.     

基于遗传算法的HMM最小错识率训练方法

最小错识率（MCE）HMM训练方法是最直接的判决训练方法之一,原理上比最大似然接方法优越得多。但是,充分发挥MCE的性能的困难在于如何将非连续的经验错识率估计映射成连续的代价函数以便采用梯度搜索技术之类的忧化方法。本文所提出的基于遗传算法的最小错识率方法（GAMCE）不但可避免MCE的缺点,而且在原理上可求得全局最优解。实验结果表明,GA_MCE比MCE好得多。     

时隙式随机争用多址系统分析方法研究

本文给出一种新的平均周期分析方法,并对时隙式随机争用多址系统进行了分析,得到了系统的信息分组发送成功的平均长度公式、信息分组发生碰撞的平均长度公式和空闲时隙的平均长度公式,并在讨论了系统的冲突分解特性后,给出了系统的吞吐量。     

遗传算法在运动目标检测中的应用

运动目标的检测在智能交通监控、车辆导航、标的正确检测十分困难，当观测采样数据受到异常污染时，辅助驾驭、高速公路上的自动收费等都有广泛的应用。运动目检测的性能对模型的微小变化不敏感。这就要求系统检测具有在其特性或参数发生摄动时仍可使品质指标保持不变的性能即鲁棒性。该文提出了在动态图像序列中基于Otsu法和遗传算法相结合的方法动态确定差分图像二值化的阈值以代替人工确定阚值的方法，从而鲁棒地检测出运动目标。     

Novel grounded and floating high order immittance simulators using OTAs and OAs

This paper proposes novel grounded and floating high order series and parallel immittance simulators using operational transconductance amplifiers (OTAs) and operational amplifiers (OAs) with a finite gain–bandwidth (GB) product. They are composed of active devices (OTAs and OAs) and resistances, and are suitable for monolithic implementation in either CMOS or bipolar technologies. They also realize both positive and negative high order immittances. The circuit characteristics can be electronically tuned by adjusting the transconductances of OTAs and the GB products of OAs. Any transfer functions are realizable using the proposed simulators. Two examples are shown, together with simulation results.     

Efficient clustering algorithms for self-organizing wireless sensor networks

Self-organization of wireless sensor networks, which involves network decomposition into connected clusters, is a challenging task because of the limited bandwidth and energy resources available in these networks. In this paper, we make contributions towards improving the efficiency of self-organization in wireless sensor networks. We first present a novel approach for message-efficient clustering, in which nodes allocate local “growth budgets” to neighbors. We introduce two algorithms that make use of this approach. We analyze the message complexity of these algorithms and provide performance results from simulations. The algorithms produce clusters of bounded size and low diameter, using significantly fewer messages than the earlier, commonly used, Expanding Ring approach. Next, we present a new randomized methodology for designing the timers of cluster initiators. This methodology provides a probabilistic guarantee that initiators will not interfere with each other. We derive an upper bound on the expected time for network decomposition that is logarithmic in the number of nodes in the network. We also present a variant that optimistically allows more concurrency among initiators and significantly reduces the network decomposition time. However, it produces slightly more clusters than the first method. Extensive simulations over different topologies confirm the analytical results and demonstrate that our proposed methodology scales to large networks.     

Ant colony optimisation–direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO–DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO–DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.