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101.
He Xinhua Gong Yunzhan 《电子科学学刊(英文版)》1996,13(1):68-73
This paper presents the techniques of verification and Test Generation(TG) for sequential machines (Finite State Machines, FSMs) based on state traversing of State Transition Graph(STG). The problems of traversing, redundancy and transition fault model are identified. In order to achieve high fault coverage collapsing testing is proposed. Further, the heuristic knowledge for speeding up verification and TG are described. 相似文献
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103.
采用RBF神经网络的状态监测数据趋势预测,通过选取状态参数、数据预处理、运用Matlab神经网络工具箱建立RBF神经网络模型.先对网络初始化,确定输入、输出和隐含层的节点数.再将网络输出结果与样本比较,根据求得误差值逐步调整隐含层神经元数量,直至误差满足实际需求为止.对网络仿真证明该法具有较高精度. 相似文献
104.
Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared. 相似文献
105.
通常空间自旋目标的3维(3D)重构都是通过对散射点轨迹进行矩阵分解的方法得到的,散射点轨迹是从雷达序列图提取并关联得到的。由于散射点提取与关联误差的存在,3D重构会出现精度下降,甚至失败的问题。另一方面,转台目标的散射点轨迹符合圆属性,这与几何投影理论认为散射点投影轨迹的椭圆属性相违背。为解决以上问题,该文提出了基于短时的空间目标3D重构算法。首先对提取的散射点轨迹进行2维圆属性拟合,使其轨迹光滑,更接近理论曲线。然后采用多视角的方法估计雷达视角(LOS),通过乘以雷达视角构成的系数,将圆属性轨迹曲线转变成椭圆属性轨迹曲线。通过对散射点椭圆属性轨迹进行矩阵分解的方法获得目标的3D结构。最后通过2个实验验证了该文所提算法的有效性。 相似文献
106.
针对非理想信道状态信息(CSI)条件下工作于underlay模式的认知无线网络(CRN)多用户下行功率分配和波束赋形研究中普遍存在的问题,包括忽略主网络(PN)对认知用户(SU)的干扰、传统的凸优化SDR方法对约束条件的近似要求以及实现算法复杂、实用性受限等,首先建立CRN模型,增添PN对SU的干扰项,而后在非理想CSI的最差条件下形成优化问题。再通过Lagrange对偶对问题的约束条件进行变换,并基于变换后的问题形式,利用上行和下行的对偶特性,引入虚拟功率,将优化问题转换为上行功率分配和波束赋形问题,进一步得到简便、快速和实用的迭代算法。数值仿真显示,算法收敛很快。并且发现非理想CSI引起的误差不仅对下行功率影响明显而且还改变优化问题的可行解区域;PN基站(PBS)的发送功率的变化对可行解区域有显著的影响。 相似文献
107.
Due to the interactions among coupled spatio-temporal subsystems and the constant bias term of affine chaos, it is difficult to achieve tracking control for the affine coupled spatiotemporal chaos. However, every subsystem of the affine coupled spatio-temporal chaos can be approximated by a set of fuzzy models; every fuzzy model represents a linearized model of the subsystem corresponding to the operating point of the controlled system. Because the consequent parts of the fuzzy models have a constant bias term, it is very difficult to achieve tracking control for the affine system. Based on these fuzzy models, considering the affine constant bias term, an H∞ fuzzy tracking control scheme is proposed. A linear matrix inequality is employed to represent the feedback controller, and parameters of the controller are achieved by convex optimization techniques. The tracking control for the affine coupled spatio-temporal chaos is achieved, and the stability of the system is also guaranteed. The tracking performances are testified by simulation examples. 相似文献
108.
Huifang Qin Yu Cao Dejan Markovic Andrei Vladimirescu Jan Rabaey 《Microelectronics Journal》2005,36(9):789-800
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper. 相似文献
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110.