数字式自动衰减器设计

文中介绍以数控衰减器ＡＤ７１１８为核心配以衰减控制码电路组成数字式自动衰减器的设计。自动衰减器量根据输入信号电平高低自动调节并具有衰减分贝值的数字显示及数字输出。     

容差扩展原则及其应用

本文提出容差扩展的三原则,并按该原则分析了电压比较器μA710(SN52510,TEXAS),提出了改进方案.按该方案集成的电压比较器FBC_(01)与同样条件下的μA710相比,成品率提高两倍,迟延时间缩小四倍,参数一致性显著提高.     

基于LM3914的电平切割细分电路

常规电平切割细分电路的细分数越高,细分电路所需的比较器也越多,会造成电睡结构烦杂,装调困难,这是限制细分数的实际原因。以点／线显示驱动器ＬＭ３９１４替代常规电平切割细分电路中的比较器阵列,可以减少比较器芯片的使用数量,提高电路的集成度,增强系统的可靠性。对ＬＭ３９１４采用级联,还可有效地提高细分电路的细分数。     

一种低失调CMOS比较器设计

本文在研究各种比较器失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器失调消除技术.该比较器由主动复位和共模箝位的预放大器和输出锁存器构成,通过负反馈自适应调整比较器输入失调电压,降低了开关电容沟道电荷注入和时钟馈通对比较器精度的影响.仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3V,调整后的比较器失调误差为34μV,比较速率100MHz.     

Contrasting reduced overshadowing and blocking.

Preexposure of a cue without an outcome (X-) prior to compound pairings with the outcome (XZ→O) can reduce overshadowing of a target cue (Z). Moreover, pairing a cue with an outcome (X→O) before compound training can enhance its ability to compete with another cue (i.e., blocking). Four experiments were conducted in a conditioned bar-press suppression preparation with rats to determine whether spacing of the X- or X→O trials would differentially affect reduced overshadowing and blocking. Experiment 1a showed that reduced overshadowing was larger with massed trials than with spaced trials. Experiment 1b found that blocking was larger with spaced trials than with massed trials. Experiments 2a and 2b indicated that these effects of trial spacing were both mediated by the associative status of the context at test. The results are interpreted in the framework of contemporary learning theories. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

基于0.18 μm CMOS工艺的超高速比较器

给出了基于TSMC 0．18μm CMOS工艺的1．8V超高速比较器的设计方案；对比较器速度和失调进行综合，设计了一个1GHz超高速低失调比较器；通过Monte Carlo仿真，验证该比较器的失调电压分布范围为-4．5～4．5mV，并进行了版图设计。该比较器应用于低电压A／D转换器设计中，可达到6位以上的精度。     

电动机保护概述

分外置控制保护器与内置控制保护器介绍了电动机的主要保护形式,并对内置控制保护器的几种方式作了进一步介绍。对所介绍的电动机保护的性能作了对比,且对BQ型防潮加热带作了独立介绍。     

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator

A high-sensitivity voltage-to-frequency converter (VFC) using an all-MOS voltage window comparator is presented in this work. The circuit is composed of one voltage-to-current converter, one charge and discharge circuit, and one all-MOS voltage window comparator. The input voltage is converted into a current which in turn triggers the charge and discharge circuit, where a built-in capacitor is driven. The voltage window comparator monitors the variated voltage on the capacitor and generate an oscillated output of which the vibration frequency is linearly dependent to the input voltage. In this way, the worst-case linear range of the output frequency of the proposed VFC is 0-55.40 MHz verified by simulations given a 0-0.9 V input range. The physical measurement of the proposed VFC shows a 0-52.95 MHz output frequency given a 0-0.9 V input range. The error in linearity is better than 8.5% while the power dissipation is merely 0.218 mW.     

数字射频存储器用GaAs超高速3bit相位ADC的设计与实现

详细讨论、分析了用于3bit相位体制数字射频存储器（DRFM）系统的3bit相位体制ADC的设计、实现及测试．利用南京电子器件研究所标准GaAs Φ76mm全离子注入工艺，采用全耗尽非自对准MESFET器件加工实现了3bit超高速相位体制ADC．测试结果表明，该电路可在2GHz时钟速率下完成采样、量化，达到1.2Gbps的输出码流速率，其瞬时带宽可达150MHz，具备±0.22LSB的相位精度．     

国产1000m/min纸机基础板的安装

本文主要就造纸机的基础板安装方案、基础板安装规范和安装实施等过程作详细介绍.