微波功率器件的滤波器测试电路

在微波电路原理和半导体器件物理的基础上,设计和模拟了三种用于微波功率器件的测试电路,并且设计了与之配套的测试夹具.采用矢量网络分析仪对该测试电路和夹具,在3～8GHz范围内进行了小信号测试.模拟和测试结果表明,采用阶梯阻抗滤波器偏置网络的测试电路性能较好,比采用扇形线偏置网络的测试电路具有更宽的带宽.该滤波器偏置电路能够用来在整个C波段,即在4～8GHz内对微波功率器件进行测试.但是,微带叉指耦合电容没有起到取代贴片隔直电容的目的,原因是该结构对参数精度要求高,而PCB制作工艺无法满足这个要求.     

基于高端FPGA的IC验证平台的电源完整性(PI)分析

通用的FPGA(Field Programmable Gate Array,现场可编程逻辑门阵列)验证平台在运行不同的应用时,其瞬态电流需求是不同的。本文以基于Xilinx公司的Virtex-4系列千万门级的FPGA高端IC验证平台为例,采用Cadence PCB PI(Power Integrity)分析软件,对多种地电平面、电容值、电容的放置位置、电容的类型等进行评估,然后通过修正电容数量和额定值,调整电容的布局以及封装等,达到符合要求的电源-地平面目标阻抗,从而将电源/地平面上的噪声降低到电源的要求范围内。本文提出的电源完整性分析方法,对其他类型的系统板级设计也有一定的指导意义。     

一种复合储能系统的改进控制方法

为了平抑新能源电源发电中产生的功率波动,文中将磷酸铁锂电池和超级电容组合,通过双向半桥变换器构成复合储能系统。根据储能元件对功率波动的频率需求不同,采用低通滤波确定各储能元件的给定功率,并用双闭环控制结构对双向变换器进行控制,同时考虑到储能元件的荷电状态对系统的影响,优化了储能系统的控制策略。Matlab/Simulink仿真结果表明,在复合储能系统稳定性提高的同时,储能电池的损耗降低,验证了所提出能量分配方案及控制策略的有效性。     

SSPD器件及其应用

以ＣＬ１２８Ｅ型ＳＳＰＤ线列阵为例,介绍了ＳＳＰＤ器件的工作原理、主要特性及其应用。     

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ～83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

采用生态设计使电子制造进入绿色循环制造时代

从生态设计的基本理念对生态设计与企业经营模式间的关系,提出若干建议;并对电子组装基板生态循环模式的建立、电子整机产品生态设计要点作了简单的分析介绍。     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

贴片电容器失效分析

采用外观检查、金相切片、SEM和EDS分析等手段,通过对贴片电容器失效实例的分析,介绍了对贴片电容器失效的分析过程与方法,得出了内部电极间的陶瓷介质裂纹存在并联电阻特性,这是导致电容器产生漏电失效的主要原因,该裂纹属制造缺陷。失效分析对贴片电容器制造工艺有质量控制作用。