一种同步光传输网络时钟故障评估模型

同步光传输网络中的时钟方案将直接影响到网络运行质量。在SSM字节保护倒换机制作用下,光传输网络中的单体设备时钟链路可以得到基本的保护。然而单体设备的故障或时钟链路的变化均存在着影响整体网络运行的风险,仅仅考虑单体的时钟保护方案远不足以形成对网络宏观的管理,在引发网络大规模时钟故障的隐患出现时更无法开展及时的排查与处理。通过概述一种基于隶属度的时钟故障评估模型,以期解决基于已知时钟方案的网络大规模时钟故障的快速分析和定位。     

单相感应电动机不同工作方式的性能比较

比较不同负载类型、不同起动方式以及斜槽数对单相感应电动机运行性能的影响,研究了恒功率负载下,单相感应电动机的运行性能与不同起动方式之间的关系;分析了电容起动方式时,不同负载类型对单相感应电动机运行性能的影响;对于恒功率负载、电容起动的单相感应电动机,探讨了斜槽程度对电动机运行性能的影响.     

幂率谱噪声的离散仿真生成

幂率谱噪声的生成一直是原子钟性能仿真领域研究的一个薄弱环节。在分析了原子钟的幂率谱噪声基础上,提出两种在时域和频域上生成幂率谱噪声的离散仿真方法,并通过仿真实现了5种幂率谱噪声的生成。仿真结果证明,该方法的实际仿真值与理论值之间的最大相对误差不超过2%,且随着取样点数N的增加,仿真值将更加接近理论值。同时由于该方法具有一般性,对于其他有色噪声的仿真生成同样具有重大的参考意义。     

基于虚拟仪器的高分辨率SoE系统设计研究

事件顺序记录系统可监测电厂事故发生前后的运行状态,其性能直接影响事故分析的及时性和准确性。将单片机实现数据采集的灵活性与LabVIEW的海量数据分析处理能力相结合,研究巨型开关量SoE系统的硬件与软件设计。数据采集和数据分析功能的分离,大幅降低了硬件设计的复杂程度,提高了SoE系统的分辨率,为建立SoE电网故障分析系统提供一种新的设计思路。     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

Chromatic Dispersion Monitoring of CSRZ Signal for Optimum Compensation Using Extracted Clock‐Frequency Component

This paper presents a chromatic dispersion monitoring technique using a clock‐frequency component for carrier‐suppressed return‐to‐zero (CSRZ) signal. The clock‐frequency component is extracted by a clock‐extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high‐speed optical communication systems.     

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system‐on‐chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.     

用VHDL实现数字时钟的设计

以一款数字钟设计为例,较详细的介绍了如何用VHDL语言设计数字电路,并给出了部分程序、仿真波形图,并在MAX＋plusⅡ中进行编译、仿真、下载。由此说明利用VHDL开发数字电路的优点。     

基于Multisim 8的数字钟的设计与仿真

应用Multisim 8进行数字钟设计与仿真。可以有效的简化设计过程,不失为一种很好的设计方法,Multisim 8作为一种高效的设计平台。其强大的虚拟仪器库和软件仿真功能,为电路设计提供了先进的设计理念和方法。     

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

As technology advances into nanometer territory, clock network layout plays an increasingly important role in determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variation. To alleviate the challenges to the existing routing algorithms due to the continuous increase of the problem size and the high-performance requirement, X-architecture has been proposed and applied to routing in that it can reduce wirelength and via counts, and thus improves the performance and routability compared with the conventional Manhattan routing. In this paper, we investigate zero skew clock routing using X-architecture based on an improved greedy matching algorithm (GMZSTX). The fitted Elmore delay model is employed to improve the accuracy over the Elmore delay model. The interactions among distance, delay balance and load balance are analyzed. Based on this analysis, an effective and efficient greedy matching scheme is suggested to reduce wire snaking and to get a more balanced clock tree. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that our algorithm (GMZSTX) achieves a reduction of 8.15% in total wirelength, 30.19% in delay and 55.31% in CPU time on average compared with zero skew clock routing in the Manhattan plane (BB+DME-2, which means using the top-down balanced bipartition (BB) method [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to generate the tree topology and using the Deferred-Merge Embedding (DME) algorithm [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to embed the internal nodes), and reduces delay and CPU time by 17.44% and 62.21% on average over the BB+DME-4 method (which is similar to BB+DME-2, but routing in X-architecture). Our SPICE simulation further verifies the correctness of the resulting clock tree.