基于并行PO/EEC的ISAR回波生成与成像仿真

为了满足基于模板的逆合成孔径雷达（ISAR）目标识别对海量高分辨模板图像的工程需求,提出了一种基于并行电磁散射特性计算技术的ISAR图像信号级仿真方法。首先,以OpenMP技术为基础采用并行物理光学和等效边缘电磁流对目标的电磁散射特性进行快速计算;其次,以步进频率波形为雷达发射波形结合目标的电磁散射特性生成了宽带雷达回波数据;最后,对使用距离多普勒算法对仿真回波数据进行处理生成ISAR像,并与点阵模型成像结果进行了对比分析。实现了对ISAR图像的信号级快速仿真,对ISAR系统设计与验证、ISAR图像解译和目标识别以及ISAR成像处理等具有重要意义。     

一种改进的外辐射源雷达直达波对消算法

针对外辐射源雷达的直达波对消技术,传统的变步长对消算法依据参考信号或对消后瞬时误差进行步长调整,对于剩余的目标回波等信号也产生了抑制效果,同时影响了直达波信号的对消效果,为此,提出了一种基于对消信号与直达波的相关性的Sigmoid函数变步长最小均方(Variable Step Size LMS based on Sigmoid function,SVSLMS)算法,根据对消后的信号与直达波的相关性进行步长调整。理论分析与仿真结果表明,改进的SVSLMS算法对直达波对消有更快的收敛速度,同时对目标回波信号的影响更小。     

卫星通信中的回波抑制与回波抵消

本文叙述了卫星通信中回波的产生及其抑制的原理，分析了ＪＵＥ－４５Ａ Ｍ Ⅱ ＩＮＭＡＲＳＡＴ－Ａ船站中回波抑制器电路，阐述了一种用横向滤波器实现的回波抵消的原理。     

具有多重PRF的雷达回波脉冲视频仿真电路的实现

在目标回波仿真原理的基础上，给出了一种新颖的脉冲多普勒雷达目标回波视频频脉冲仿真电路。通过计数分频和计数延时技术，该电路获得了大范围可变的脉冲重复频率和高精度的脉冲时延，能对距离不断变化的动目标进行实时模拟。给出了电路的结构框图，并对设计原理作了必要说明。     

相关法旁瓣对消抗有源压制干扰分析及仿真

介绍了一种相关法旁瓣对消抗干扰技术,对其系统组成及基本工作原理进行了分析,建立了系统电路仿真模型,最后,给出了此系统对几种有源压制干扰的对消结果。结果表明,该系统对抗有源压制干扰有很好的效果。     

基于AWG/RTSA的PD雷达信号模拟和相参分析方法

针对脉冲多普勒(PD)雷达的回波特点和相参特点,分析了回波模拟的难点.在其传统回波模拟和相参分析方法基础上,结合现代电子测量仪器在任意波形产生和实时频谱技术的应用,提出了一种基于现代任意波信号发生器的PD雷达回波模拟方法和基于现代实时频谱分析仪的相参分析方法.经过实验验证,该方法可有效提高PD雷达的调试效率.     

自适应旁瓣对消在数字阵列雷达中的工程实现

自适应旁瓣对消是雷达抗有源干扰的有效方法。文中简要介绍了自适应旁瓣对消的基本原理,旁瓣对消模块在某雷达的应用,推导出便于工程实现的理论公式。在实际工作中能满足雷达系统抗干扰性能指标的要求。     

一种非相参雷达回波信号模拟器的设计

分析雷达回波特性,从非相参信号模拟开始,提出一种雷达回波模拟器的实现方法。该方法可以利用已知或计算机产生的目标信息运算获得回波信号数据,通过FPGA或DSP芯片控制DDS产生中频回波信号。这种方法具有极大的灵活性和通用性,只要改变计算机回波信号计算模型或参数,即可实现不同回波信号的模拟。     

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.

New high accuracy CMOS current conveyors

In this paper, a new CMOS CCII⁺ is proposed. The circuit is characterized by high precision in voltage tracking and exhibits very low input resistance. An adaptive voltage offset cancellation methodology is introduced and then applied to the proposed circuit. As a result, a higher accuracy CCII⁺ is presented. For both circuits, the voltage offset cancellation is independent of the input current and voltage. To demonstrate the strength of the proposed architectures, fair comparisons with Liu and Yodprasit CCII realizations are held.