基于数学形态学的医学图像分割

采用分水岭算法对医学图像进行分割,并针对其容易产生过分割的缺点,作了两点改进：首先对原始图像进行自适应加权的多尺度形态滤波,然后引入浮点活动图像作为分水岭算法的输入。实验表明,该方法算法简单,能有效地抑制过分割现象,得到较好的分割效果。     

高性能HPOR CORDIC算法及实现

CORDIC算法在通信和图像处理等各个领域有着广泛的应用,但是浮点CORDIC由于迭代延时大且实现复杂没有得到很好的应用,本文提出了一种修正浮点CORDIC算法：高精度顺序迭代HPORCORDIC。该算法以接近定点的运算代价完成浮点运算迭代,运算速度和硬件实现规模与定点CORDIC相当,运算精度与浮点CORDIC相当,克服了定点CORDIC运算精度差,浮点CORDIC迭代延时大、实现复杂的问题。该算法既可用于通用微处理器的设计,也可用于高性能DSP的设计。     

A Hardware Acceleration Platform for Digital Holographic Imaging

This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm which transforms an interference pattern captured on a digital image sensor into visible images. Focus in this work is to maximize computational efficiency, and to minimize the external memory transfer overhead, as well as required internal buffering. The paper presents an efficient processing datapath with a fast transpose unit and an interleaved memory storage scheme. The proposed architecture results in a speedup with a factor 3 compared with the traditional column/row approach for calculating the two-dimensional FFT. Memory sharing between the computational units reduces the on-chip memory requirements with over 50%. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom designed FPGA platform and integrated in a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.     

ASIC Design of Floating-Point FFT Processor

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.     

X-DSP浮点乘法器的设计与实现

为了满足高性能X-DSP浮点乘法器的性能、功耗、面积要求,研究分析了X型DSP总体结构和浮点乘法器指令特点,采用Booth 2编码算法和4∶2压缩树形结构,使用4级流水线结构设计实现了一款高性能低功耗浮点乘法器。使用逻辑综合工具Design Compiler,采用第三方公司0.13μm CMOS工艺库,对所设计的乘法器进行了综合,其结果为工作频率500MHz,面积67529.36μm2,功耗22.3424mW。     

Optimizing precision overhead for x86 processors

It is a major challenge for a Java JIT compiler to perform single-precision floating-point operations efficiently for the x86 processors. In previous research, the double-precision mode is set as the default precision mode when methods are invoked. Sophisticated approaches then use heuristic approaches to optimization by considering the trade-offs between roundings and mode switches. However, this convention introduces redundant mode switches across method boundaries. Furthermore, methods that include both single- and double-precision operations cannot switch the mode, even if single-precision operations are dominant. We propose a new approach to these problems. We eliminate redundant mode switches by ignoring the default precision mode and calling a method in the same precision mode as the caller. For methods that include both single- and double-precision methods, we reduce the overhead of rounding by isolating code segments of a given method that should be executed in the single-precision mode. We implemented our approach in IBM's Just-in-Time compiler, and obtained experimental results demonstrating that, in SPECjvm98, it consistently shows the best performance in any configuration of benchmark programs, inline policies, and processor architectures compared with previous research approaches. Copyright © 2004 John Wiley & Sons, Ltd.     

单节拍浮点运算神经元的组合逻辑设计

介绍了通用神经计算机CASSANDRA-中单节拍浮点运算神经元的硬件设计方法.基于通用超曲面神经元模型,以组合电路与EPROM查表分别实现浮点数加法、乘法及p次幂运算,从而实现了单节拍内完成浮点运算|W(X-Y)|p的神经元组合逻辑设计.该设计使通用神经计算机硬件具有更强的适应能力和更好的网络性能     

Model adjointization and its cost

1 Introduction With great development of observation and sampling techniques, the research of inverse problems, e.g., data assimilation and remote sensing inversion, is becoming a frontier and focus in some disciplines such as atmospheric sciences and oceanography. Most optimization methods, which depend on first or higher order derivatives of consid-ered functions, are efficient ways to solve such large-scale inverse problems. Compared with other differentiation techniques, e.g., divided dif…     

快速浮点加法器的优化设计

运算器的浮点数能够提供较大的表示精度和较大的动态表示范围,浮点运算已成为现代计算程序中不可缺少的部分.浮点加法运算是浮点运算中使用频率最高的运算,因此,浮点加法器的性能影响着整个CPU的浮点处理能力.文中从分析浮点加减操作的基本算法入手,介绍了一种新的算法,即三数据通道浮点加法算法,并着重介绍了整数加法器和移位器的设计,对32位浮点加法器的设计进行了优化.     

基于FPGA的浮点FIR滤波器的设计与实现

针对短波宽带接收机系统中信号动态范围大的特点，自定义了24位的浮点格式，并采用流水线技术设计了该格式浮点数的加法和乘法运算单元。在分析了各种FIR滤波器优缺点的基础上．结合FPGA的特点给出了转置型FIR校正滤波器设计方案。最后，以数据率为2．5MS／S的宽带信号为输入，Ahera公司的EP2S60F672C5芯片为硬件平台仿真实现了10通道短波宽带接收机的250阶FIR校正滤波器，最高运行速率达到130MHz以上。