Challenges of 22 nm and beyond CMOS technology

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new devi...     

纳米MOSFET寄生电阻模型分析

随着器件尺寸的缩小,寄生电阻对器件性能的影响不可忽视,为准确预测器件的寄生电阻并了解器件参数对寄生电阻的影响,需要有准确的寄生电阻模型。该文分析了短沟道寄生电阻模型,研究了短沟道寄生电阻模型在栅压较小时与模拟结果存在较大误差的原因,并对模型进行了改进。最后分析了器件参数对寄生电阻的影响,提出未来减小寄生电阻需要和可能采取的措施。     

基于FPGA的全数字脉宽调制器

为了解决传统的脉宽调制(PWM)信号电路的设计复杂、噪声大及抗干扰能力差等缺点,设计一种全数字脉宽调制器(DPWM),采用先进的现场可编程逻辑器件(FPGA)和硬件描述语言(VHDL),有效地控制cs时钟信号的上升沿和下降沿和脉冲宽度,可以很好地解决像增强器的光晕现象,扩大其动态范围;通过仿真实验,验证了全数字脉宽调制器(DPWM)控制系统具有控制灵活精确、设计简单易修改、抗噪抗干扰能力强等特点;FPGA可重复擦写,当需要实现其它功能时,只需在程序上改动即可,可方便地嵌入需要调节控制的各个系统,加快系统开发和利用.     

基于调用门的进程隐藏技术

Rootkit是黑客入侵系统后保留后门常用的一项技术,而Rootkit的过人之处就在于它的隐形技术。论文主要介绍了目前Windows下常见的进程隐藏方法,并分析了现有方法的局限性,提出一种新的方法,该方法通过调用门的方式来修改进程链表和进程的访问令牌,从而达到进程隐藏和提升进程权限的目的,该攻击方法隐蔽性更强,能有效对抗常规的安全检测技术。最后用实验证明了此方法的有效性。     

轨道交通站台安全门控制系统

轨道交通站台安全门作为公共安全防护设备,广泛应用在地铁、轻轨等轨道交通中的高架和地面站台上,具有节能、环保和安全功能。因此它在设计、制造、安装过程中需要充分考虑其自身的可靠性及乘客安全、行车安全。本文将对安全门系统的网络、控制及软件三方面进行详细论述。     

中国传统建筑门的形态研究

中国古建筑的门,不仅仅只是一种建筑形态,而且是人们心目中的一个重要概念。因为概念与原型之间的互动,在有关门的具体的建筑活动中,这些形而上的观念又不断显露并发展,促进着门本身在艺术上的进步。文章从文化和心理方面等多方面对中国古建筑的门进行了分析研究。     

SOPC外扩SDRAM的设计要点分析

针对SDRAM正常工作所需要的条件较为严格,介绍将SDRAM接入SOPC的设计方法及要点。重点介绍在PCB设计阶段所要注意要点,以及根据不同的FPGA和SDRAM来选择时钟频率,最后详细介绍如何计算锁相环的相移,使得输出的SDRAM时钟和控制器时钟同步以确保SDRAM正常工作。     

When do extra majority gates help? Polylog (N) majority gates are equivalent to one

Suppose that a Boolean functionf is computed by a constant depth circuit with 2 ^m AND-, OR-, and NOT-gates—andm majority-gates. We prove thatf is computed by a constant depth circuit with AND-, OR-, and NOT-gates—and a single majority-gate, which is at the root.One consequence is that if a Boolean functionf is computed by an AC⁰ circuit plus polylog majority-gates, thenf is computed by a probabilistic perceptron having polylog order. Another consequence is that iff agrees with the parity function on three-fourths of all inputs, thenf cannot be computed by a constant depth circuit with AND-, OR-, and NOT-gates, and majority-gates.     

A variable-precision square root implementation for field programmable gate arrays

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.Notation S_j square root digit of weight 2^–j - S _j {–1, 0, 1} - S[j] computed square root value as of stepj - S _j ^s sign bit in the representation ofS _j in sign and magnitude form - S _j ^m magnitude bit in the representation ofS _j in sign and magnitude form - w[j] residual at stepj in two's complement carry-save representation - a sum vector in the carry-save representation of 2w[j] - b carry vector in the carry-save representation of 2w[j] - a _i bit of weight 2^–i in the sum vector,a - b_i bit of weight 2^–i in the carry vector,b - T[j]=–S[j – 1]s_j – s _j ² 2^–(j+1) T _i bit of weight 2^–i inT     

浮动电极对屏蔽栅沟槽型MOSFET特性的影响

提出了在屏蔽栅沟槽型MOSFET(SGT)的沟槽侧壁氧化层中形成浮动电极的结构,通过改善电场分布,优化了特征导通电阻与特征栅漏电容。在传统SGT结构的基础上,仅通过增大外延层掺杂浓度,改变浮动电极的长度和位置以及氧化层厚度,最终得到击穿电压为141.1 V、特征导通电阻为55 mΩ·mm²、特征栅漏电容为4.72 pF·mm^-2的浮动电极结构。与相同结构参数的SGT结构相比,在击穿电压不变的条件下,浮动电极结构的特征导通电阻降低了9.3%,Baliga优值提升了13%,特征栅漏电容降低了28.4%。