在协议集成测试系统上开展路由协议测试

在分析路由协议的特性及其测试需求的基础上，提出利用窗口黑盒来描述被测协议，利用多通道测试方法扩展对被测实现的控制和观察，通过扩充参考实现增强系统的测试能力。将这些理论，技术应用于系统中，对路由协议开展了有效的测试活动，为国产高性能路由器的开发提供了有力的支持，也进一步增强了PITS系统的功能和适用性。     

欧洲无线DSL的发展现状及市场前景

对欧洲的立法者来说，目前最为关注的课题之一便是如何解决数字鸿沟这一困扰欧洲大陆信息与通信技术整体发展水平的矛盾。向人们提供高速因特网接入服务是消除数字鸿沟的有效手段，而无线数字用户线技术以及其成低、通信质量好、覆盖范围大及灵活性等优势成为宽带接入技术中的佼佼者，并获得很多欧洲国家电信运营商的青睐。     

液压集成块校核软件的编制和应用

本文叙述了液压集成块校核软件的编制思想和方法，并重点介绍了编制过程中所使用的相关技术，同时给出部分源程序。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

一种以太网兼容的综合话音/数据传输协议

本文提出一种与现有以太网兼容的综合话音/数据协议.描述了协议模型及实现方法.并用PASCAL语言在IBM-PC机上模拟研究了该协议的性能.模拟结果表明,该协议能满足话音的实时要求,性能良好,且数据传输性能没有明显下降.协议克服了以太网传输话音延迟不确定的缺点.     

数据通信网综合网管的设计分析

结合TMN电信管理网的体系结构．对数据通信网综合网管的结构和功能进行了分析。     

Numerical modelling of the propagation of fast landslides using the finite element method

This paper proposes a two‐dimensional (2D) model for the analysis of the propagation of fast landslides involving a fluidized material such as debris and mud flows, flowslides and avalanching flows. The model is based on the Navier–Stokes depth‐integrated equations. To incorporate the effect of steep slopes and centrifugal forces due to the high velocities characterizing the flowslides and the bed curvature, a curvilinear system of reference is used. The corresponding equations of motion are complemented by depth‐averaged constitutive equations and bed friction laws. The resulting set of differential equations are solved using the two‐step Taylor–Galerkin algorithm. This algorithm has been used by the authors to solve hydraulic and dam‐break problems using the finite element method. Owing to the importance of the source term compared to the advection component, the proposed algorithm follows a splitting scheme using a fourth‐order Runge–Kutta method for integrating the friction and slope components. The performance of the overall approach has been checked in a number of examples. The analysis of the results provides insights into the key elements of the model and shows the adequacy of the method to solve real problems where merging and splitting of the flow occur. Copyright © 2004 John Wiley & Sons, Ltd.     

西门子全集成自动化理念初探

系统阐述了全集成自动化理念的内涵，指出其特点在于统一的数据管理、统一的编程组态、统一的通讯以及无与伦比的开放性，其中采用WINCC与STEP7两个软件进行了说明，井提出全集成自动化应用将是今后自动化技术发展应用的方向。     

射频识别模块SMC51489在门禁系统中的应用

射频识别系统一般由三部分组成:电子标签(射频卡)、读取器和天线.正确快速的识别电子标签的标签号码,是门禁系统发挥其功能的先决条件.以无源低频射频卡识别模块SMC51489为例,介绍了对射频卡信息读取的原理和方法,并给出了相应的软件编程.实验证明该模块不仅具有较大的读卡距离,而且工作可靠.