A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.     

垂直纳米线晶体管的制备技术

对目前垂直纳米线晶体管的制备技术进行了综述.首先根据器件结构取向介绍了纳米线晶体管的分类,即水平纳米线晶体管和垂直纳米线晶体管,比较了这两类不同结构晶体管的优缺点,阐述了垂直纳米线晶体管的优势及其潜在应用价值.重点介绍了两种主流的垂直纳米线晶体管的制造方法,即自下而上方法和自上而下方法,自上而下方法则又分为后栅工艺和先栅工艺.随后详细比较了它们之间的不同.最后,对垂直纳米线晶体管制造过程中的工艺挑战进行了分析,提出了几种可行的解决方案,并预测了垂直纳米线晶体管未来的发展趋势,特别是在低功耗器件及3D存储器等方面的发展走向.     

Improving Memory Efficiency of Dynamic Memory Allocators for Real‐Time Embedded Systems

Dynamic memory allocators for real‐time embedded systems need to fulfill three fundamental requirements: bounded worst‐case execution time, fast average execution time, and minimal fragmentation. Since embedded systems generally run continuously during their whole lifetime, fragmentation is one of the most important factors in designing the memory allocator. This paper focuses on minimizing fragmentation while other requirements are still satisfied. To minimize fragmentation, a part of a memory region is segregated by the proposed budgeting method that exploits the memory profile of the given application. The budgeting method can be applied for any existing memory allocators. Experimental results show that the memory efficiency of allocators can be improved by up to 18.85% by using the budgeting method. Its worst‐case execution time is analyzed to be bounded.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

Influence of metal gate and capping film stress on TANOS cell performance

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.     

270 MHz Full HD H.264/AVC High Profile Encoder with Shared Multibank Memory‐Based Fast Motion Estimation

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high‐quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real‐time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.     

Uniform Approximation of Discrete-Time Periodically Varying Systems

It is shown that the elements of a large class of discrete-time periodically varying nonlinear input-output maps can be uniformly approximated arbitrarily well, over infinite time intervals, using a certain structure that can be implemented in many ways using, for example, radial basis functions, polynomial functions, piecewise linear functions, sigmoids, or combinations of these functions. For the special case in which these functions are taken to be certain polynomial functions, the input-output map of our structure is a generalized finite discrete-time Volterra series. Results are given for the case in which inputs and outputs are defined on the integers. The case in which inputs and outputs are defined on the nonnegative integers is also addressed.     

Stabilization of space charge polarization in ion-dispersed gate dielectric layer of organic transistors by ultraviolet illumination for write-once read-many memory

In this work, a new type organic field effect transistor (OFET) based write-once read-many memory (WORM) device was developed. The device uses an ultraviolet (UV) cross-linkable matrix polymer mixed with ionic compounds to form an ion-dispersed gate dielectric layer. Under an applied gate voltage bias, migration of cations and anions in opposite directions forms space charge polarization in the gate dielectric layer, resulting in change of the electrical characteristics. It is shown that, with UV illumination to cross-link the matrix polymer, the formed space charge polarization can be stabilized. Therefore, the OFET can be operated as a WORM with the applied voltage bias to define the polarization and in turn the stored data, and the UV illumination to stabilize the stored data.     

Effect of interfacial fluorination on the electrical properties of the inter-poly high-k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al₂O₃ and HfO₂ IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO₂ possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al₂O₃ dielectric is more effective to promote the IPD characteristics than fluorination of the HfO₂ dielectric. For future stack-gate flash memory application, the fluorinated Al₂O₃ IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO₂ IPD due to superior insulating properties.     

一种新颖的模糊形态联想记忆网络

模糊形态联想记忆网络FMAM具有较强的抗膨胀或腐蚀噪声能力，且可以模糊性解释。但抗混合噪声的能力很弱。而在实际中，随机噪声往往是混合型的，既有膨胀又有腐蚀噪声。为此提出了一种基于尺度空间的模糊形态联想记忆网络，并分析了其抗膨胀／腐蚀噪声和抗随机噪声的能力，它提高了自联想FMAM的抗随机噪声能力。通过仿真实验验证了该方法具有良好的性能。