高速数据采集系统中缓存区的设计

本文讨论了高速数据采集系统的设计，对如何利用低速ＳＲＡＭ来替代ＤＡＳ中的高速ＲＡＭ作了重点分析     

一种相变存储器读出电路及其快速读出方法

针对大规模相变存储器所具有的寄生电容大、可能出现读破坏现象等特性,提出了一种读电压模式的相变存储器读出电路及其快速读出方法。基于SMIC 40nm CMOS工艺的仿真结果表明,在2.5V电源电压下,该方法可以在90ns的读出周期内正确读出位线寄生电容为30pF的存储单元数据,同时,该读出周期随位线寄生电容的减小而减小。另外,该方法可以和传统的Burst等快速读出方式并存,非常适用于带数据预读机制的高端存储器技术。     

数字射频存储器在脉冲多普勒雷达噪声干扰中的应用

采用数字射频存储器(DRFM)技术的噪声干扰机,具有瞄频精度高、噪声带宽窄、干扰功率利用率高的特点,可对脉冲多普勒(PD)雷达实施有效干扰。介绍了DRFM干扰机的组成和工作原理。并分析了瞄频误差和寄生信号的产生以及它们对干扰噪声的影响。     

Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

两种LTE上行SC-OFDMA信号生成方式

首先讨论了Long Term Evolution（LTE）上行传输方案的提出的需求背景,然后简要介绍集中式单载波和分散式单载波概念,研究了它们分别在时域和频域的生成方式,最后分析比较两种方案的优缺点。     

基于RTX与反射内存的实时支撑系统设计

随着半实物仿真系统的发展,基于Windows+以太网的仿真模式不能满足仿真系统对实时性的要求,为达到提高仿真系统整体实时性的目的,采用了基于RTX+反射内存网的模式,改进了仿真系统的运行平台和数据传输模式,改进了仿真设备的接入方式,规划了改进模式后的仿真框架,搭建了该模式下的示例工程。该系统的仿真步长可以达到1 ms以内,能够满足半实物仿真的需求。     

超高温环境下航天器数据记录器防热结构设计

通过用ANSYS软件热仿真数据存储器在1100℃下工作半小时后壳体的温度分布情况,介绍了怎样设计数据记录器的壳体,可使存储器部分有效地回收。并通过有限元分析的直接法,列出了各种材料上所设节点的温度计算矩阵方程,用MATLAB计算出各节点温度结果,再与用ANSYS软件仿真出来的试验结果进行比较,确定试验结果的正确性一一即壳体结构在超高温下工作的可行性。     

Growth ambient on memory characteristics in Au nanoclusters embedded in high-k dielectric as novel non-volatile memory

In this work, we report on the findings of the effects of different ambient on memory characteristics of a floating gate memory structure containing HfAlO control gate, self-organized Au nanoclusters (NCs), and a HfAlO tunnel layer deposited by the pulsed-laser deposition. The optimized fabrication environment has been found and stored charge density up to 10¹³ cm⁻² has been achieved. As the sizes of the Au NCs are smaller than 4 nm, they may be potentially used in multilayer-structured multi-bit memory cell.