A CMOS Low-Noise Instrumentation Amplifier Using Chopper Modulation

This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal band hereby ensuring overall low noise performance. The resulting equivalent input referred noise is approximately 7 nV/ for a chopping frequency of 20 kHz. The amplifier operates from a modest supply voltage of 1.8 V, drawing 136 A of current thus consuming 245 W of power. The gain is 72.5 dB over a 4 kHz bandwidth. The inband PSRR is above 90 and the CMRR exceeds 105 dB.Jannik Hammel Nielsen was born in Nuuk, Greenland, in 1972. He received the M.Sc. and Ph.D. degrees in electrical engineering in 1999 and 2004 respectively, from the Technical University of Denmark. He is presently employed as a postdoctoral researcher at ØrstedDTU.His main research interests are in low-voltage, low-power analog systems, medical electronics and data converters.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I²L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ØrstedDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

一种应用于数字电视中的CMOS宽带高线性LNA设计

基于TSMC 0.13μm CMOS工艺设计了一款应用于数字电视中的CMOS宽带高线性低噪声放大器。该电路采用传统宽带低噪声放大器的改进结构。为了提高LNA的线性度,采用伏尔特拉级数分析了电路的非线性分量,并修正了传统的噪声抵消电路用于抵消整个电路的非线性分量。基于TSMC 0.13μm CMOS工艺对其进行了设计,仿真结果表明：此LNA在50-860 MHz频带内,增益为12.7-13.3 dB,噪声系数最小仅为1.2 dB,在1.2 V的电源电压下,工作电流为12.2 mA,并且其输入三阶交调点为9.7~14.2 dBm,取得了较高的线性度。     

X波段低噪声放大器的设计

为了实现X波段的低噪声放大器,介绍了按最小噪声系数设计,采用两级级联,利用Eudyna公司的HEMT晶体管设计制作的低噪声放大器。通过专用微波电路设计软件(AWR),对该电路的稳定系数、功率增益、噪声系数、驻波比、匹配网络等进行了仿真分析。根据分析结果制作的X波段LNA取得了如下指标:在9.5～10.5 GHz频带内,功率增益大于22 dB,噪声系数小于1.5 dB,输入输出驻波小于1.7。     

基于CMOS工艺的RFID双频低噪声放大器设计与仿真

设计出一种可应用于RFID系统,同时工作在915 MHz和2.45 GHz的双频段低噪声放大器.该设计以最大程度降低噪声为目标,采用并联LC网络替代传统单一高感值电感,并引入电流复用技术,最终实现高增益低功耗的双频段低噪声放大器的设计目标.仿真结果如下:在915MHz和2.45GHz的频率下,噪声系数均小于0.6dB;S(1,1)小于—15dB;S(2,2)小于—11dB;输入驻波比≤1.4;输出驻波比≤1.8;1dB压缩点约为—16.5dBm.仿真结果表明,在两个频段中的测试结果均优于预期指标的要求,为实际双频段低噪声放大器的设计及优化提供参考。     

双极晶体管关键参数的研究

本文基于双极晶体管的工艺,就如何对电流增益和特征频率两个参数进行优化研究.首先对其进行了器件工艺模拟分析优化,得到模拟特征频率在10 GHz,电流增益为160,而后进行了流片,通过测试得到特征频率为9.5 GHz,电流增益在160以上,最后进行了测试结果和模拟结果的比较分析.     

一种新型GPS前端CMOS低噪声放大器的设计

介绍了一种工作于GPS L1频带的新型低噪声放大器的设计方案.电路运用电流镜结构进行电流放大,并利用偏置电流复用技术减小功耗.该放大器工作在1.575 GHz时, 电源电压为1.5 V的情况下噪声系数为1.06 dB,电压增益为23 dB,1 dB压缩点为-17.36 dBm,S11<-10 dB,电流为4.6 mA.     

S 波段 GaAs 超低噪声限幅低噪声放大器芯片的研制

本文将限幅器嵌入到了低噪声放大器的输入级匹配电路,使得整体限幅放大电路的噪声系数为低噪声放大器的最小噪声系数而不需再加上限幅器的损耗,从而有效降低了整体限幅低噪声放大器的噪声系数。 在此基础上,设计并实现了一款 S 波段限幅低噪声放大器芯片,实现了超低噪声与高耐功率的性能。 测试结果表明,该款芯片在目前相近频段所有限幅低噪声放大器产品中噪声系数最小。 在2. 7 GHz~ 3. 5 GHz 工作频带内,实测噪声系数 NF≤0. 85 dB,增益≥29 dB,带内增益平坦度≤±0. 3 dB,静态工作电流≤25 mA,1 dB 压缩点输出功率≥8 dBm。 在耐功率50 W(250 μs 脉宽、25%占空比)下试验 30 min 后不烧毁,恢复到常温时,噪声几乎无变化。 芯片尺寸为 3 450 μm×1 600 μm×100 μm。     

20~26 GHz硅基氮化镓可变增益低噪声放大器

基于100 nm硅基氮化镓(GaN)工艺,本文设计并实现了一款工作频段为20～26 GHz且增益平坦的可变增益低噪声放大器(VGLNA).该放大器采用三级共源级级联来实现高增益,并通过调节第二、第三级的栅极偏置实现增益控制.测试结果表明,该放大器在工作频段内实现了超过20 dB的增益可变范围和±1.5 dB的增益平坦度,在增益可变范围内功耗为126 mW至413 mW.在最大增益状态下,该放大器在整个频段内可实现大于20 dB的小信号增益且噪声系数(NF)为2.95 dB至3.5 dB,平均输出1dB压缩点(OP1dB)约为14.5 dBm.该芯片的面积为2 mm~2.     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

Design of an analog front-end for ambulatory biopotential measurement systems

A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented.The front-end circuit is capable of amplifying and conditioning different biosignals.To optimize the power consumption and simplify the system architecture,the front-end only adopts two-stage amplifiers.In addition, careful design eliminates the need for chopping circuits.The input-referred noise of the system is only 1.19μVrms (0.48-2000 Hz).The chip is fabricated via a SMIC 0.18μm CMO...