大功率UPS的并联控制技术

提出了一种新的N 1三相大功率UPS的并联控制方案，并且在4台40KVA三相在线式UPS上进行了实验研究，实际运行结果证明采用此方法可以获得良好的静态与动态特性。     

逆变电源并联技术

逆变器并联是提高电源系统可靠性 ,扩充系统容量的有效方式。本文介绍了逆变电源并联的原理、技术要求和特点。对当前采用的逆变电源并联方案进行了总结和分类。在此基础上详细分析了各种并联方案的特点和内在关系 ,指出了逆变电源并联技术的发展趋势。     

集群计算机上基于BSP模型的并行算法及其程序设计

文章分析了BSP模型和集群计算机的特点，给出了在集群计算机根据BSP模型设计并行算法及其软件的原则，举例说明了利用BSP模型代价公式定性分析并行算法性能的方法，并利用实验结果验证了得出的结论。结果表明模型的成功地抽象出了集群计算中影响算法性能的诸种因素，并通过代价公式反映出来，利用代价公式可以基本准确地估计并行算法代价，这对集群计算机上的并行算法及其软件及设计和优化具有重要的指导意义。     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

基于事例学习的建筑结构的虚拟实现

提出基于事例学习的目标规划问题,并进一步研究了建模思想的可行性和建模方法的可操作性。利用知识工程、机器学习理论,人工智能技术来存贮和运用专家的经验,实现了在虚拟环境中建筑结构设计、施工,设备的仿真试验,并可对初学者或尚无经验的设计、施工者进行培训学习。该项研究为目标规划问题开辟了基于事例学习的模型生成途径。     

A stochastic realization algorithm via block LQ decomposition in Hilbert space

A stochastic realization problem of a stationary stochastic process is re-visited, and a new stochastically balanced realization algorithm is derived in a Hilbert space generated by second-order stationary processes. The present algorithm computes a stochastically balanced realization by means of the singular value decomposition of a weighted block Hankel matrix derived by a “block LQ decomposition”. Extension to a stochastic subspace identification method explains how the proposed abstract algorithm is implemented in system identification.     

计算机高速并行通信的实现方案

利用CPLD芯片实现单片机与ISA总线接口之间的高速并行通信，给出系统的总体设计方法及程序框图。采用这种通信方式，在12MHz晶振的MCS51单片机控制的数据采集系统中，可以满足与PCI04 ISA总线接口实时通信的要求，通信速率达200khit／s。在开发工具MAX plusⅡ下，完成了整个设计的输入、编译和仿真，达到了预期效果。本设计方案能够推广应用到计算机的高速并行通信中。     

多码CDMA系统中联合并行干扰抵消与迭代信道估计方法

本文针对多码CDMA系统提出了一种联合并行干扰抵消与迭代信道估计方法。该方法首先通过导频符号对信道进行估计，然后使用RAKE接收机后的软信息对信道参数进行修正，最后通过并行干扰抵消(PIC)去除多码干扰(MCI)。仿真结果表明，经过多次迭代后，该方法可显著地降低多码CDMA系统的误比特率平台。本文同时还给出了信道估计质量、码道数和PIC次数对多码CDMA系统性能的影响。