Variation-aware approaches with power improvement in digital circuits

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.     

MPLS技术在唐山有线电视综合信息网数据平台中的设计与应用

MPLS技术是一项具有多协议支持的技术，它综合利用了网络核心的交换技术和网络边缘的IP路由技术各自的优点，它将标记分配给多协议的数据桢以便在基于我展品信元的网络中传输。它能够提供现有传统IP路由技术所不能支持的要求保障QoS的业务，通过MPLS技术，我们可以提供各种新兴的增值业务，有效的实施流量工程和计费管理措施，扩展和完善更高等级的基础服务。     

一种片上网络路由测试方法研究

对片上网络路由器的结构进行了分析,建立了相应的故障模型.针对此故障模型结合内建自测试,提出了一种基于量子遗传算法的测试矢量传递路径寻优方法.该算法具有收敛速度快,精度高等优点.最后通过对测试故障覆盖率和测试时间进行分析表明这种测试方法具有较高的故障覆盖率、较少的测试时间.     

Real-time 3D multi-pedestrian detection and tracking using 3D LiDAR point cloud for mobile robot

Mobile robots are used in modern life; however, object recognition is still insufficient to realize robot navigation in crowded environments. Mobile robots must rapidly and accurately recognize the movements and shapes of pedestrians to navigate safely in pedestrian-rich spaces. This study proposes real-time, accurate, three-dimensional (3D) multi-pedestrian detection and tracking using a 3D light detection and ranging (LiDAR) point cloud in crowded environments. The pedestrian detection quickly segments a sparse 3D point cloud into individual pedestrians using a lightweight convolutional autoencoder and connected-component algorithm. The multi-pedestrian tracking identifies the same pedestrians considering motion and appearance cues in continuing frames. In addition, it estimates pedestrians' dynamic movements with various patterns by adaptively mixing heterogeneous motion models. We evaluate the computational speed and accuracy of each module using the KITTI dataset. We demonstrate that our integrated system, which rapidly and accurately recognizes pedestrian movement and appearance using a sparse 3D LiDAR, is applicable for robot navigation in crowded spaces.     

Area Analysis for On-chip Routers with Different Data-link Widths

Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.     

数据驱动片内多核通信结构

针对当前条件下多核处理器遇到的通信瓶颈问题,设计了一种采用数据驱动机制的片内多核通信结构,该结构包括数据驱动模块和片上路由器.数据驱动模块用来进行数据完备性检测;片上路由器则实现处理器核间的通信及"簇"间通信.在Altera公司的CycloneIII开发板上使用NIOS软核构建了多核系统进行了验证.实验结果表明,本设计可以有效的实现多核片内通信,具有很好的可扩展性.     

基于SOA架构的法院档案管理信息系统研究与实现

针对法院业务复杂度高,技术环节多,系统庞大等特点,基于SOA架构的应用集成使得应用系统可以实现灵活的业务流程,快速适应需求变化的业务发展需要。基于SOA架构的法院档案管理系统提出了针对法院档案管理中的应用集成解决方案,研究并实现了应用集成平台。该系统能够实现法院中案件的统计、业务数据和业务流程的无缝连接等,有效解决法院里各种信息的孤岛问题,实现协同统计和量刑。     

自适应光电混合互连分流结构建模与性能分析

针对片上光电混合互连网络(hybrid optoelect ronic network-on-chip,HONoC)拥 塞控制与自适应能力差、无法实现光电联合仿真等问题,提出一种适用于可重构阵列处理器 的自适应光电混合互连分流结构,在此结构上设计了自适应分流路由算法与一种低损耗无阻 塞的5端口光路由器,并搭建了基于System verilog与Verilog的光电混合互连功能仿真与 性能统计模型。实验结果表明,在边缘节点阻塞的情况下所设计的路由算法避免拥塞能力平 均提升了17.5%,光路由器所需交叉波导与微环谐振器数量大幅减少,平均光路由器级插入 损耗仅为0.522 dB,所设计的光电混合互连性能统计模型具有支持 设计拓扑、结构和路由策 略等功能,并且可以对资源使用、功耗开销、插入损耗等性能进行统计分析。     

一种基于微环的新型4×4非阻塞光路由开关

光互连技术因诸多特性优于电互连而成为片上多核互连最具前景的解决方案。为了提高片上光互连网络架构的性能,采取光器件模块搭建的方法,提出了一种基于微环的新型4×4光路由开关,仅用7个微环构建的拓扑结构便实现了4个双向端口的非阻塞交换,降低了功耗和面积;波导交叉的数量减少到6个,优化了插入损耗。结果表明,该结构相对于经典结构光器件的功耗节省了约8%,光互连层的插入损耗降低了约7%。     

IPv6应用通道过渡技术部署关键问题及组网研究

分析了在下一代互联网过渡技术部署下实现电信运营商应用通道业务所面临的关键问题;基于不同的业务实现模型和技术实现难度,研究并对比了过渡技术部署下的应用通道多种组网方案;最后,提出了应用通道业务在过渡技术部署下的演进策略.