钛合金的银脆,镉脆敏感性及其控制

利用慢应变速率拉伸技术（ＳＳＲＴ），并结合恒载实验，较全面地研究了Ｔｉ－６Ａｌ－４Ｖ合金的银脆行为、固态与液态镉脆行为，确定了应变速率、接触条件、热处理制度、试样取向、温度等因素对Ｔｉ－６Ａｌ－４Ｖ合金银脆与镉脆敏感性的影响，探讨了Ｎｉ阻挡层对控制Ｔｉ－６Ａｌ－４Ｖ合金和ＴＣ１１合金银脆开裂的作用。     

专用集成电路CAT技术的进展

本文简单地回顾了提高VLSI测试效率所采用的一些手段,讨论了在ASIC测试问题研究中出现的一些新观点、新方法、新动向,以及所取得的成果。在此基础上,文章阐明了ASIC测试技术的发展方向,并着重论述了可望在未来得到发展的,针对ASIC的功能测试方法。     

由1,4-萘醌催化合成1,4-二烷氧基萘-2,3-二甲腈

研究了以 1 ,4-萘醌为原料 ,通过溴代、氰化和 O-烷基化三步合成 1 ,4-二烷氧基萘 -2 ,3 -二甲腈。在溴代反应中以溴化试剂代替液溴 ;在氰化和 O-烷基化反应中以溴化十二烷基三甲基铵 (DTMAB)和聚乙二醇(PEG)作为相转移催化剂 ,并采用正交设计法考察了相转移催化剂、固体碱、反应温度等因素对反应的影响 ,其中氰化产物收率达 88.7%。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme

Pseudo-random testing techniques for mixed-signal circuits offer several advantages compared to explicit time-domain and frequency-domain test methods, especially in a BIST structure. To fully exploit these advantages a suitable choice of the pseudo-random input parameters should be done and an investigation on the accuracy of the circuit response samples needed to reduce the risk of misclassification should be carried out. Here these issues have been addressed for a testing scheme based on the estimation of the impulse response of the device under test (DUT) by means of input-output cross-correlation. Moreover, new acceptance criteria for the DUT are suggested which solve some ambiguity problems arising if the classification of the DUT as good or bad is based on a few samples of the cross-correlation function. Examples of application of the proposed techniques to real cases are also shown in order to assess the impact of the measurement system inaccuracies on the reliability of the test.     

数值方法确定地基承载力特征值的探讨

介绍了目前地基承载力的确定方法，研究了数值计算的可行性，并对其数值计算地基承载力的可靠性进行验证，指出应进一步完善确定地基承载力的方法，更好地解决群桩基础承载力的确定问题。     

Studies on the corrosion behavior of cerium-implanted zircaloy-4 with GAXRD

In order to study the influence of cerium ion implantation on the aqueous corrosion behavior of zircaloy-4, specimens were implanted by cerium ions with a fluence range from 1×10¹⁶ to 1×10¹⁷ ions/cm² at maximum 150°C, using MEVVA source at an extracted voltage of 40 kV. The valence and elements penetration distribution of the surface layer were analyzed by X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES) respectively. Glancing angle X-ray diffraction (GAXRD) was employed to examine the phase transformation due to the cerium ion implantation in the oxide films. Three-sweep potentiodynamic polarization measurement was employed to value the aqueous corrosion resistance of zircaloy-4 in a 1 N H₂SO₄ solution. It was found that a significant improvement in the aqueous corrosion behavior of zircaloy-4 implanted with cerium ions compared with that of the as-received zircaloy-4. The improvement effect will declined with raising the implantation fluence. The bigger is the fluence, the less is the improvement. Finally, the mechanism of the corrosion behavior of the cerium-implanted zircaloy-4 is discussed.     

Simulation of cup-cone fracture using the cohesive model

The cohesive model is used for the prediction of the crack path during stable crack extension in ductile materials. The problem of crack-path deviation is investigated by means of simulation of crack propagation in a round tensile bar. The respective phenomenon is known as cup-cone fracture. It is shown that the model is able to predict the failure mechanism, which consists of normal fracture in the center and combined normal/shear fracture in the so-called “shear lips” at the specimen’s rim. The damage evolution and crack path predicted by the model are presented. The effect of the normal and shear failure parameters on the crack-deflection point and several aspects of the finite element mesh are discussed.     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.