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本文提出了油井稳定生产状态下的脉冲试井数学模型,利用时间和空间叠加原理求得其解析解。并用非线性回归分析方法来进行脉冲试井分析。     

Physicochemical characteristics and leachability of scale and sludge from Bulalo geothermal system, Philippines

Scale and sludge from Bulalo geothermal field, Philippines, have been characterized by whole rock analysis, radioactivity counting, size analysis, light microscopy, scanning electron microscopy, and X-ray diffraction. Their leachability was assessed by regulatory leaching procedures and by sequential extraction. Both scale and sludge consisted mostly of oxides of Si, Al, and Fe with no radionuclides detected. The scale had 10% S content. Sulfides and silicates were important phases in both samples having size ranges from submicron to 2 mm. Geothermal soils at Bulalo have higher than normal soil levels of As, S, Cu, Cr, Zn, and Pb but regulatory leaching tests indicated that these elements are not released. However, the sequential extraction showed that As, Cu, and Zn were leachable under extreme conditions.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

New and used temporal models: An issue of time

TheSpecial Issue on Applications of Temporal Models raises many issues of time: What are the important properties of time? How can time be best represented? How can one reason about time-dependent properties? What are the important directions of temporal research? This introductory piece very briefly surveys the current wide variety of temporal models, temporal reasoning methods, and applications to time-varying phenomena. Promising areas of investigation such as the verification of concurrent systems, knowledge-base representation methods, and dealing with theFrame Problem pass in fleeting review. Brief introductions to each of the works in the volume close the section.     

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.     

On the Yustova threshold plates

A response to criticism of threshold plates for the study of color vision developed at the Mendeleev All-Russia Research Institute of Metrology and published in 1994 is presented. The critics base their conclusions on colorimetric testing and the examination of the plates. In response to the article by M. V. Danilova and J. D. Mollon [4]. __________ Translated from Izmeritel’naya Tekhnika, No. 1, pp. 37–39, January, 2007.     

用双向扭转圆柱组合螺旋弹簧实现扭矩测试

利用单个圆柱螺旋扭转弹簧扭转原理,给出了一种用双向扭转圆柱组合螺旋弹簧实现扭矩测试的方法。根据扭转弹簧模型,给出了预紧力、加载的证明,并对实验结果进行分析;该结构用于扭矩测试系统既实用可靠,又简单易加工;降低了测试系统的成本,具有很高的实用价值。     

一种新型微处理器功能验证

文中介绍一种新型微处理器的验证方法，并对相关的一些验证策略进行深入的讨论。     

From the individual element test to finite element templates: Evolution of the patch test

This paper starts a sequence of three articles that follow an unconventional approach in finite element research. The ultimate objective is to construct high-performance elements and element-level error estimators for those elements. The approach takes off from our previous work in high-performance elements and culminates with the development of finite element templates. The present paper concentrates on the patch test and evolved versions of the test that have played a key role in this research. Following a brief review of the historical roots, we present the Individual Element Test (IET) of Bergan and Hanssen in an expanded context that encompasses several important classes of new elements. The relationship of the IET to the multielement forms A, B and C of the patch test and to the single-element test are investigated. An important consequence of the IET application is that the element stiffness equations decompose naturally into basic and higher-order parts. The application of this decomposition to the “sanitization” of the non-convergent BCIZ element is described and verified with numerical experiments. Two sequel papers in preparation are subtitled ‘the algebraic approach’ and ‘element-level error estimation’. These apply the fundamental decomposition to the derivation of templates for specific mechanical elements and to the construction of element-level error estimators, respectively.     

Experience with Applying Formal Methods to Protocol Specification and System Architecture

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.