液压集成块校核软件的编制和应用

本文叙述了液压集成块校核软件的编制思想和方法，并重点介绍了编制过程中所使用的相关技术，同时给出部分源程序。     

轧机主传动万向联轴器辊端接头结构探讨

分析了衬板槽平面与叉头十字轴孔轴线的相对位置对辊端接头应力的影响 ,研究了轧辊扁头与衬板之间间隙所产生的冲击和应力集中 ,讨论了辊端接头中部过渡段结构对应力分布和制造质量的影响。提出辊端接头结构设计的优化方案     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

射频识别模块SMC51489在门禁系统中的应用

射频识别系统一般由三部分组成:电子标签(射频卡)、读取器和天线.正确快速的识别电子标签的标签号码,是门禁系统发挥其功能的先决条件.以无源低频射频卡识别模块SMC51489为例,介绍了对射频卡信息读取的原理和方法,并给出了相应的软件编程.实验证明该模块不仅具有较大的读卡距离,而且工作可靠.     

面向WLAN的MPC852T嵌入式系统设计

MPC852T是Motorola新近推出的MPC866/MPC859T家族中面向低端的一款通信处理器.嵌入式Linux由于其费用低廉及开放源码而具有广阔的发展前景.文中在分析了MPC852T通信处理器和嵌入式Linux操作系统的基础上,将二者结合给出了一种嵌入式硬件系统的设计与实现,以及该硬件系统在无线局域网WLAN中的一种应用.实践证明,该硬件系统具有性能稳定、廉价、可扩展性强、适用面广等优点.     

实现CDMA最佳多用户检测的神经网络方法

提出并讨论了两种实现码分多址系统中最佳多用户检测的神经网络方法。一种基于离散Ｈｏｐｆｉｅｌｄ神经网络，另一种基于采用反向传播算法的多层感知器神经网络。理论分析和计算机模拟都证实了这两种神经网络方法的可行性，优越性和实用性。前者适用“固定”用户情况；后者既可用于“固定”用户吼适用于移动用户的情况，因而在未来的ＣＤＭＡ个人通信网中有较好的应用前景。     

通用串行总线(USB)数据传输模型

USB作为一种数据传输接口，了解它的通信传输机制是正确利用USB利用数据传输的基础，分层次结构对USB数据传输模型加以分析，可以使读者建立起USB体系结构、通信模型和总线事务的框架和概念，并最终对USB传输工作流程有一个清晰的认识。     

异构数据的管理方法及异构数据源的集成研究

工程应用中软件工具的多样性和设计活动的分散性形成了大量异构数据。本文分析了传统的异构数据管理方法的不足，提出使用数据库系统的文件系统结合的管理方法。针对此方法下所形成的异构数据源问题，给出了基于J2EE规范的数据访问对象抽象工厂解决方案。     

实用宽带新技术

简要介绍了三种宽带新技术及其应用，包括替代五类线的VDSL，可解决HFC上行噪音漏斗效应的SCDMA技术以及利用电源线传输高速数据的PLC技术。这些新技术由于具有较高的性能价值比和广阔的应用前景，受到了广泛的关注。