Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

Data-driven Distributionally Adjustable Robust Chance-constrained DG Capacity Assessment

Moving away from fossil fuels towards renewable sources requires system operators to determine the capacity of distribution systems to safely accommodate green and distributed generation（DG）. However, the DG capacity of a distribution system is often underestimated due to either overly conservative electrical demand and DG output uncertainty modelling or neglecting the recourse capability of the available components. To improve the accuracy of DG capacity assessment, this paper proposes a distributionally adjustable robust chance-constrained approach that utilises uncertainty information to reduce the conservativeness of conventional robust approaches. The proposed approach also enables fast-acting devices such as inverters to adjust to the real-time realisation of uncertainty using the adjustable robust counterpart methodology. To achieve a tractable formulation, we first define uncertain chance constraints through distributionally robust conditional value-at-risk（CVa R）, which is then reformulated into convex quadratic constraints. We subsequently solve the resulting large-scale, yet convex, model in a distributed fashion using the alternating direction method of multipliers（ADMM）. Through numerical simulations, we demonstrate that the proposed approach outperforms the adjustable robust and conventional distributionally robust approaches by up to 15% and 40%, respectively, in terms of total installed DG capacity.     

计及分布式电源与需求响应的智能配电系统安全域

中国城市电网正逐步发展为智能配电网,系统运行环境将更为复杂。配电系统安全域(DSSR)是指导配电网安全运行的新理论,文中考虑智能配电网的2个主要元素——分布式电源(DG)和需求响应(DR),从传统的负荷视角研究DSSR。首先,分析含DG和DR的配电系统安全性特点,给出相应的数学表达式,然后建立考虑DG和DR的DSSR数学模型。其次,通过观测算例电网的DSSR的二维截面图像,分析DG和DR对DSSR的作用机理,并基于此给出系统规划运行的指导建议。提出的DSSR的负荷视角与现有调度人员习惯一致,对于仍以负荷供电为主、以DG和DR服务为辅的城市配电网,可作为实用的安全运行分析工具。     

Applications of one-cycle control to improve the interconnection of a solid oxide fuel cell and electric power system with a dynamic load

Adding distributed generation (DG) is a desirable strategy for providing highly efficient and environmentally benign services for electric power, heating, and cooling. The interface between a solid oxide fuel cell (SOFC), typical loads, and the electrical grid is simulated in Matlab/Simulink and analyzed to assess the interactions between DG and the electrical grid. A commercial building load profile is measured during both steady-state and transient conditions. The load data are combined with the following models that are designed to account for physical features: a One-Cycle Control grid-connected inverter, a One-Cycle Control active power filter, an SOFC, and capacitor storage. High penetration of DG without any power filter increases the percentage of undesirable harmonics provided by the grid, but combined use of an inverter and active power filter allows the DG system interconnection to improve the grid tie-line flow by lowering total harmonic distortion and increasing the power factor to unity.     

Time stepping in discontinuous Galerkin method

The time discretization in the Discontinuous Galerkin (DG) scheme has been traditionally based on the Total Variation Diminishing (TVD) second-order Runge-Kutta (RK2) scheme. Computational efficiency and accuracy with the Euler Forward (EF) and the TVD second-order RK2 time stepping schemes in the DG method are investigated in this work. Numerical tests are conducted with the scalar Burgers equation, 1-D and 2-D shallow water flow equations. The maximum Courant number or time step size required for stability for the EF scheme and RK2 scheme with different slope limiters are compared. Numerical results show that the slope limiters affect the stability requirement in the DG method. The RK2 scheme is generally more diffusive than the EF scheme, and the RK2 scheme allows larger time step sizes. The EF scheme is found to be more efficient and accurate than the RK2 scheme in the DG method in computation.