无线环境下一种新的证书状态查询方案

分析有线环境现有证书状态查询方案的基础上,提出了一种对传统的 O C S P进行了改进的方案-用户端部分缓存的ocsp方案,并将其与其他证书状态查询方案进行了比较。该方案借鉴了哈希链的思想,具有很高的安全性,可以有效减少用户端及服务器端的运算量,降低带宽负荷,适合用作无线环境下的证书状态查询方案。     

List partitions

By definition, apartition of a list is a division of that list into nonempty contiguous segments. Many programming and operations research problems can be specified in terms of list partitions, and we present a hierarchy of theorems for deriving programs from such specifications. Throughout, reasoning is conducted in an equational style using the calculus for program synthesis developed by Bird and Meertens.Supported by a BP research studentship.     

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

A hierarchical design methodology for full-search block matching motion estimation

Many useful DSP algorithms have high dimensions and complex logic. Consequently, an efficient implementation of these algorithms on parallel processor arrays must involve a structured design methodology. Full-search block-matching motion estimation is one of those algorithms that can be developed using parallel processor arrays. In this paper, we present a hierarchical design methodology for the full-search block matching motion estimation. Our proposed methodology reduces the complexity of the algorithm into simpler steps and then explores the different possible design options at each step. Input data timing restrictions are taken into consideration as well as buffering requirements. A designer is able to modify system performance by selecting some of the algorithm variables for pipelining or broadcasting. Our proposed design strategy also allows the designer to study time and hardware complexities of computations at each level of the hierarchy. The resultant architecture allows easy modifications to the organization of data buffers and processing elements-their number, datapath pipelining, and complexity-to produce a system whose performance matches the video data sample rate requirements.     

基于Intel AVX2的LTE DFT和IDFT快速算法

通用处理器（GPP,General Purpose Processor）技术的快速发展,为LTE基带信号实时处理提供了一条新的途径。在LTE系统中,DFT和IDFT分别是手机上行发送和基站上行接收中的重要模块。根据3GPP协议,LTE DFT和IDFT处理点数是复合数,文章通过混合基算法以取代直接计算算法,并充分利用GPP平台大存储量的优势及Intel AVX2指令进行并行计算能力,最终使得该算法实现平均每处理1点仅耗时2个cycles,接近FPGA硬件处理性能,满足了LTE系统的实时性要求。经验证,基于GPP平台的DFT和IDFT模块运行结果正确,并且耗时极短。     

从《日本食品中农业化学品残留肯定列表制度》探讨我国输日农产品的应对措施

日本政府将在2006年5月29日起实施《日本食品中农业化学品残留肯定列表制度》。现对该制度的修改动因、修改过程、修改前后内容的变化以及对中国农产品出口的影响作一介绍,并提出了建议和基层相关企业宜采取的应对措施。     

综合核心处理系统评价工具设计

综合核心处理系统是航空电子综合化模块化的关键支撑技术.如何对其性能指标进行评价是一个非常重要的理论和工程问题.首先建立了综合核心处理器模型、任务模型.然后基于ARINC 653标准建立了双层分区调度模型,该模型实现了不同安全关键级别应用软件之间的隔离.根据离散事件仿真方法,建立了系统仿真模型.在此基础上编制了基于Visual C++平台的系统仿真程序,最后提取ICD接口控制文件进行了实例仿真,分析了任务的可调度性及系统的实时性,其结果对指导新一代航电系统设计具有重要意义.     

基于双链式存储的可靠通信网合并

本文介绍图的双链式存储结构在可靠通讯网合并算法中的应用.