Cost efficiency comparison of four video-based techniques for assessing upper arm postures

Many video-based techniques for assessing postures at work have been developed. Choosing the most appropriate technique should be based on an evaluation of different alternatives in terms of their ability to produce posture information at low input costs, i.e. their cost efficiency. This study compared four video-based techniques for assessing upper arm postures, using cost and error data from an investigation on hairdressers. Labour costs associated with the posture assessments from the video recordings were the dominant factor in the cost efficiency comparison. Thus, a work sampling technique associated with relatively large errors appeared, in general, to be the most cost-efficient because it was labour-saving. Measurement bias and other costs than labour cost for posture assessment influenced the ranking and economic evaluation of techniques, as did the applied measurement strategy, i.e. the numbers of video recordings and repeated assessments of them. PRACTITIONER SUMMARY: The cost efficiency of four video-based techniques for assessing upper arm postures was compared. Work sampling techniques were in general more cost efficient than continuous observations since they were labour-saving. Whilst a labour cost dominated the comparison, 'hidden costs', bias and measurement strategy also influenced this dominance.     

Fully differential CMOS CCII based on differential difference transconductor

This paper presents a new CMOS fully differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 380 μA. The application of the FDCCII to realize variable gain amplifier, fully differential integrator, and fully differential second order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 μm technology.     

CMOS current feedback op amp-based chaos generators using novel active nonlinear voltage controlled resistors with odd symmetrical characteristics

Novel grounded and floating CMOS active nonlinear resistors with odd symmetrical characteristics are designed. The nonlinear resistors are then incorporated into two chaotic oscillator circuits based on a CMOS current feedback op amp (CFOA). The slopes of both the negative and positive segments of the nonlinear characteristics are voltage controlled, allowing for a wide range of dynamic behaviour to be observed and easily tuned in a period doubling route to chaos. Nonlinear current–voltage characteristics are derived in a piecewise-linear form and shown possibly to be modelled using a cubic polynomial approximation. PSPICE simulations using a standard 2.0 μm technology file and numerical simulations of the derived chaotic mathematical models are included.     

Transient analysis of a PV power generator charging a capacitor for measurement of the I–V characteristics

Measuring the I–V characteristics is of high importance since it can be considered as a quality and performance certificate for each PV generator. The most precise and inexpensive measuring method is represented in capacitor charging by the PV generator. Using the equivalent circuit of the PV generator with a capacitor as load and applying transient analysis on the circuit, we obtain the capacitor charging voltage and current as a function of time, as well as their differentials as a function of short circuit current and capacitor size. The derived equations facilitate the calculation of proper capacitance size for measuring the I–V characteristics, and considers the acquisition speed of the measuring system as demonstrated through two measurement samples in this paper. The capacitor size is directly and indirectly proportional to the short circuit current and open circuit voltage of the PV generator, respectively. Accordingly, the paper presents a capacitance calculation chart, which enables selecting the correct capacitance for measuring the I–V characteristics by a computerized data acquisition system.     

Low-Voltage digitally controlled fully differential current conveyor

Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of this DCFDCC. The proposed DCFDCC operates under low supply voltage of /spl plusmn/1.5 V. The realization of the DCFDCC using the new CDN is presented by two approaches. First approach has linearly proportional current gain with the digitally controlled parameter of the CDN, while the second approach exhibits current gain between terminals X and Z greater than, or equal to, one. Applications of the DCFDCC in realizing second order universal active filter and variable gain amplifier are given. PSPICE simulation confirms the performance of the proposed blocks and its applications.     

On the Electromagnetic Interference Fringes Method in Geophysical Prospecting Applications

The method of electromagnetic interference fringes for the prospecting of conductive subsurfaces inside the earth is reviewed. The fields radiated by an electrically small horizontal loop situated on the earth's surface are derived and expressed in terms of different interfering wave components. The variable distance interference fringes (VDIF) method and the variable frequency interference (VFIF) method of prospecting are considered, and an interpretation procedure using the data obtained from both methods is suggested.     

Efficient Hybrid Linear Massive MIMO Detector Using Gauss–Seidel And Successive Over-Relaxation

The initial solution of a massive multiple-input multiple-output (M-MIMO) detector for uplink (UL) is greatly influence the balance between the bit error rate (BER) performance and the computational complexity. Although the maximum likelihood (ML) detector obtains the best BER performance, it has an extremely high computational complexity. Iterative linear minimum mean square error (MMSE) detector based on the Gauss–Seidel (GS), the successive over-relaxation (SOR), and the Jacobi (JA), obtains a good performance-complexity profile when the base station (BS)-to-user-antenna-ratio (BUAR) is large. However, when the BUAR is small, the system suffers from a considerable performance loss. In this paper, a hybrid detector based on the joint GS and SOR methods is proposed where the initial solution is determined by the first iteration of GS method. Numerical results show a considerable complexity reduction and performance enhancement using the proposed GS-SOR method over all methods when the BUAR is small.

     

A Generalized {\mathcal{H}}_{2} Filtering of Uncertain Discrete-Time Singular Systems with Time-Varying Delays

In this paper, the problem of delay-dependent robust filtering of linear discrete-time singular systems with time-varying delays and polytopic uncertainties is thoroughly investigated. We employ a linear regular filter to ensure its practical implementation. We establish the filter admissibility condition, then using an improved augmented Lyapunov–Krasovskii functional, we develop new delay-dependent filtering design conditions based on generalized H₂{\mathcal{H}}_{2} performance criteria and without relying on overbounding for both the nominal and uncertain cases. Seeking computational convenience, all the developed results are cast in the format of strict linear matrix inequalities (LMIs) and a numerical example is presented.     

High IIP3 and Low-Noise CMOS Mixer Using Non-linear Feedback Technique

A third-order intermodulation cancelation technique using a non-linear feedback is proposed to design a low-power low-distortion mixer in a 65 nm standard CMOS technology. The IM3 cancelation is achieved by estimating distorting error at a non-linear feedback element and subtracting it from the input. The linearization technique is utilized in the input trans-conductance of the mixer. The circuit functionality is analyzed using Volterra series. The covering frequency range of the mixer is 800 MHz to 5 GHz. The technique increases the input-referred third-order intercept point (IIP3) and input 1 dB compression point to +16.4 dBm and −1.87 dBm, respectively. It obtains a gain of 9 dB and an input-referred noise of 1.84 nV/?{}/\sqrt{}Hz while consumes 8.75 mA from 1.2 V supply. The layout of the mixer occupies 0.315 mm × 0.296 mm of silicon area.