基于哈佛结构的单周期堆栈处理器设计

本文设计了一种基于Forth语言的堆栈式16位单周期处理器,该处理器含有深度为32的数据栈、返回栈和哈佛存储结构,其指令集包括29条指令,它的所有指令均在单个周期内执行完成．此处理器在Xilinx公司的XC5VLX110T FPGA开发板上实现的最高时钟频率为162．7M Hz ．本文首先介绍了此处理器的设计方法、整体结构和指令集,然后分析指令单周期执行的机制,最后给出了处理器的仿真和综合结果及其分析．     

叠层压敏电阻器的近期研制动向

从构成叠层压敏电阻器的生片材料（材料晶粒大小、生片厚度）、内电极材料、叠层结构和表面处理等方面，介绍叠层压敏电阻器的近期研制动向。     

IPv6网络与业务演进策略分析

随着IPv4地址的加速消耗,IPv4网络和业务向IPv6过渡已经势成必然,但在向IPv6演进的过程中,存在IPv6内容源缺乏,IPv4/IPv6互通困难,网络设备对IPv6支持程度参差不齐等各种问题。电信运营商必须结合自身网络和业务特点,选择合适的过渡技术和策略,平滑地向IPv6演进。本文首先简要介绍各种IPv6过渡技术,然后从电信运营商的角度,分析对比网络和业务向IPv6演进的各种策略,并指出演进过程中存在的一些困难以及解决办法。     

FTTx系统的IPv6解决方案简介

在介绍IPv6发展演进趋势的基础上,从业务透传、业务感知、IPv6协议栈支持等方面介绍了FTTx系统的IPv6改造阶段,最后给出了烽火通信FTTx系统IPv6的解决方案。     

基于路径标识的多路径域间路由的开发与实现

针对现有网络架构中路由扩展性方面的问题日益严重,目前提出一种基于路径标识的多路径域间路由方案,可提高域间路由可扩展性和可靠性,但该研究只停留在理论阶段。现对基于路径标识的多路径路由协议进行了开发与实现,针对域间路由协议BGP的控制层和基于Linux内核的转发层进行了具体模块的结构分析和开发,并进行了功能性测试。结果显示,开发系统可以实现路径标识路由和多路径路由的功能。     

外延用300mm重掺B Si衬底中热致微缺陷研究

研究了重掺B对300 mm直拉Si衬底中热致微缺陷的影响.通过800℃/4～16 h+1 100℃/16 h的低-高两步退火处理发现,与普通(CZ)Si片相比,重掺B(HBCZ)Si片体内生成了高密度的热致微缺陷--体微缺陷(BMDs);B浓度的不同对BMDs的形态也有重要影响,重掺B Si片中出现杆状层错,随着B浓度的增加,层错密度增加,尺寸减小.研究表明,重掺B对BMDs的促进作用主要归功于B原子促进了氧沉淀的异质形核并由于原子半径效应使得这些核心较容易长大,而晶体中初始氧含量不是重掺B促进氧沉淀的主要因素.     

3G移动可视电话系统设计

介绍了3G移动可视电话的设计架构模式,基于Window CE操作系统,结合VTApp、3G-324M协议栈、音视频设备驱动、RIL和双端口RAM等相关模块,实现了可视电话这一复杂的多媒体应用系统的运行,描述了相关模块的工作原理与设计思路,并通过对呼出流程图加以介绍的方式,对可视电话系统的运行流程加以阐述。     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

3-DMCM实用化的进展

介绍了 3- D MCM的四种封装模式的应用实例 ,详细讨论了各种模式的工艺 ,优点及存在的问题。 3-D MCM是未来微电子封装的发展趋势。