双MicroBlaze软核处理器的SOPC系统设计

设计了一款基于双MicroBlaze软核处理器、面向嵌入式领域的SOPC系统,在信息处理繁忙的情况下,实现两软核处理器之间的同步、通信和中断功能,提高信息吞吐率和系统灵活性,降低设备尺寸。两处理器之间通过Mutex模块实现同步功能,通过Mailbox模块实现通信和中断功能,通过共享BRAM模块实现大块通信功能,并进行了有效的功能验证。该SOPC系统在XUPV5－LX110T开发板上得到验证。测试结果表明,两软核处理器之间有效地实现了同步,通信和中断功能,达到了预期的效果,验证了方案的有效性。     

A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices

This paper presents a new method and results from measurement of internal parameters of programmable nanoscale circuits, namely Xilinx FPGA devices and especially Zynq SoC devices designed on 28 nm TSMC’s technology and older 45 nm Spartan 6 device as well as Xilinx Virtex product lines. The method utilizes a new undersampling approach for frequency measurement and an easy way of processing BRAM data streams. The proposed flexible circuits have been used in various measurements of timing parameters and delays in FPGAs, including measurements or detection of the aging issues. The paper presents results of measurements under various core voltage values as performed on selected Xilinx FPGA platforms, including key results about limited usability of the latest 28 nm devices under accelerated conditions and possibility of studying or mitigating aging effects in FPGAs. The paper presents rare results of experiments, real measurements and data available from current as well as previous technology nodes and it attempts to uncover new facts and areas of the latest high-end technologies, including the area of aging and degradation processes in general. The new methodology, presented approach and results can also be used in various dependable systems, including selected aerospace, medical, automotive or transportation ones. It is also directly and easily applicable to modern processor and multicore systems.     

Analysis and performance evaluation of HYPERchannel access protocols

HYPERchannel [1,3,5,7] is a local network configuration with random access to the global transmission medium and with ‘Carrier Sense’ techniques. Conflicts are resolved by a fixed priority scheduling of retransmissions.This paper presents a performance evaluation of HYPERchannel access protocols for different types of user systems. Analytical results and asymptotic relations are obtained for the throughput of HYPERchannel under different load characteristics.The fixed priority rule for retransmissions discriminates against low priority users; a modification of the access scheme (‘Fair HYPERchannel’) is proposed which compensates for this undesirable effect. The performance of this new protocol version is also evaluated.In a final section, the access schemes of HYPERchannel are compared with similar access protocols.     

一种FPGA中BRAM36k的设计方法

BRAM以阵列的方式排布于FPGA内部,是FPGA实现各种存储功能的主要部分。FPGA通过BRAM以及可编程逻辑资源给用户提供各种不同的存储资源。介绍了FPGA其中可编程存储模块BRAM36k的具体功能以及实现方法。该模块支持多种地址和数据位宽纵横比组合、多种读接口和写接口数据带宽转换,支持奇偶校验bit写入和读出。最后对模块的功能进行了功能级仿真验证,仿真结果符合预期设计目标。     

FPGA块存储器的多位翻转容错设计

在高可靠性航空航天、航空电子设备和军用应用中,辐射引发的多比特翻转(MBU)成为FPGA存储器的一个主要的可靠性问题;传统的单比特错误纠正(SEC)和双比特错误检测(DED)无法对FPGA存储器发生的MBU故障提供防护,引发存储器的存储故障;为了减少MBU造成的影响,设计了RM(2,5)编码防护系统对FPGA块存储器进行容错防护,实现了单个码字小于4位的翻转错误的纠正;对RM编码系统进行了三模冗余设计,解决了RM码不具备抗辐射的缺陷;设计的RM(2,5)编译码模块在Xilinx Virtex-5 FPGA中实现,编码模块频率以225.284 MHz运行,占用LUT资源1.33％;通过理论分析和硬件实验表明,该错误检测与纠正(EDAC)系统能够纠正4位以下的翻转,提高FPGA存储器的可靠性.