Programming models for hybrid CPU/FPGA chips

Designers of embedded and real-time systems are continually challenged to meet tighter system requirements at better price-performance ratios. Best-practice methods have long promoted the use of commercial-off-the-shelf components to reduce design costs and time to market, but creating COTS components that are reusable in a wide range of applications remains difficult. In part, the challenge lies in satisfying the contradictory design forces of generalization and specialization. Systems designers are all too familiar with the tension these opposing forces cause in trying to balance cost versus performance. Adopting COTS components reduces costs and time to market but often fails to meet the most demanding performance requirements; custom-designed components can achieve significantly higher performance but at greater development costs and longer times to market. Emerging hybrid chips containing both CPU and field-programmable gate array (FPGA) components are an exciting new development. They promise COTS economies of scale while also supporting significant hardware customization. Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.     

Boundary scan test standards

I give an overview of several standards defining test technology based on boundary scan. The Test Technology Technical Council (MC), an IEEE Computer Society technical committee, sponsors these standards.     

SUAVE: extending VHDL to improve data modeling support

Our aim in the SUAVE (SAVANT and University of Adelaide VHDL Extensions) Project is to improve support for high-level modeling and reuse in VHDL. A number of previous proposals also address these goals. SUAVE extends the language with object-orientation and genericity features and generalizes some existing features. Extending VHDL in this way has the side effect of improving its expressiveness at all abstraction levels. We adapted most of the added features from Ada-95, largely for the same reasons they are included in that language     

Protected shared variables in VHDL: IEEE standard 1076a

In this article, we show a variety of problems that can arise from unprotected concurrent access to shared variables and review the idea of monitors, which forms the basis of the proposed language change. We then describe the new language feature, protected types, and give some guidelines on using them for hardware modeling. We also include examples to illustrate their use     

Programming models for hybrid FPGA-cpu computational components: a missing link

Emerging hybrid chips containing cpu and FPGA components are an exciting new development promising commercial off-the-shelf economies of scale, while also supporting hardware customization.