Electrical properties of N2O/NH3 plasma grownoxynitride on strained-Si

Growth of ultrathin (<100 Å) oxynitride on strained-Si using microwave N₂O and NH₃ plasma is reported. X-ray photoelectron spectroscopy (XPS) results indicate a nitrogen-rich layer at the strained-Si/SiO₂ interface. The electrical properties of oxynitrides have been characterized using a metal-insulator-semiconductor (MIS) structure. A moderately low value of insulator charge density (6.1×10¹⁰ cm^-2) has been obtained for NH₃ plasma treated N₂O oxide sample. Nitrided oxide shows a larger breakdown voltage and an improved charge trapping properties under Fowler-Nordheim (F-N) constant current stress     

An Improved Method for Load Taxonomy Using Sample Shifting Technique and Signature Analysis

This paper illustrates an improved method of classification of electrical appliances, particularly for domestic loads, to construct load taxonomy on the basis of their signature analysis. Each electrical load is characterized by its own distinct signature and hence load signature analysis is useful in monitoring the health of the equipment, power quality, in determining individual energy usage etc. type of services. On the other hand, load taxonomy classifies these loads in several clusters on the basis of some features extracted from their signatures. In traditional methods of construction of load taxonomy, different signature patterns based on power metrics, V-I trajectories, Eigen vectors, etc. In this proposed method, with the adoption of sample shifting technique the required number of feature extraction is reduced to a lower value to find out various signature patterns than those are required in traditional load taxonomies. Moreover, a better taxonomy, having well separated groups of loads is achieved with lower number of extracted features.     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

Temperature behavior and compensation of light-emitting diode

This letter offers a fresh insight into the behavior of light-emitting diode (LED) over temperature. Theoretically and by measurement, it has been shown that equi-intensity curves in the diodes current-voltage plane are nearly a straight line over a very wide range of temperatures. Based on this property, bias voltage and resistance value of a bias circuit have been realized and practical measurement shows the peak-to-peak light intensity variation decreases from 99 % (in case of fixed current bias) to 6 % over the temperature range of -20 C to +80 C for the LED IN6092. This circuit uses no separate temperature sensor or compensating mechanism, but responds directly to the junction temperature of the diodes. This prevents any error caused by temperature gradient, or by self-heating due to power dissipation in the diode.     

Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field

The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field.     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

Formulae for determining heterodyne system spurious frequencies that coincide with desired output frequency

In this paper, formulae to determine the lowest order and other higher order spurious frequencies that coincide with desired output signal frequencies of mixers have been derived. The proposed formulae give general expressions that are suitable for any order of heterodyne mixing. The formulae have been verified using a suitable example and compared with the simulation results obtained through the radio frequency simulation software of Advanced Design System. The formulae directly reveal the order of the troublesome spurious frequencies that the designers would encounter in heterodyne systems. In comparison with these direct formulae, the results of existing spurious analysis software are based on the maximum order of simulation carried out. Based on these simulations, the coinciding spurious components have to be manually sorted out. Proposed formulae are quick tools used by the microwave system and circuit designers for choosing and finalizing heterodyne frequencies in their designs without the need for any simulations.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.