Recombination lifetime profiling in very thin Si epitaxial layersused for bipolar VLSI

A recently proposed measurement technique (P. Spirito and G. Cocorullo, IEEE Trans. Electron Devices, vol.ED-32, no.9, p.1708-13, 1985) to evaluate the recombination lifetime along epitaxial layers is used to characterize the quality of very thin Si epitaxial layers used for bipolar technology. The experimental results show the ability of the technique to give accurate and detailed information on the quality of epilayers that could be useful in monitoring and improving the growth process. The experimental results show that the lifetime values in thin epilayers are not correlated with doping profiles in the same layers; moreover, they are only slightly dependent on different processes used to make the test devices     

Adaptive Census Transform: A novel hardware-oriented stereovision algorithm

This paper presents a new hardware-oriented approach for the extraction of disparity maps from stereo images. The proposed method is based on the herein named Adaptive Census Transform that exploits adaptive support weights during the image transformation; the adaptively weighted sum of SADs is then used as the dissimilarity metric. Quality tests show that the proposed method reaches significantly better accuracy than alternative hardware-oriented approaches. To demonstrate the practical hardware feasibility, a specific architecture has been designed and its implementation has been carried out using a single FPGA chip. Such a VLSI implementation allows a frame rate up to 68 fps to be reached for 640 × 480 stereo images, using just 80,000 slices and 32 RAM blocks of a Virtex6 chip.     

Thermo-optic design for microwave and millimeter-wave electromagnetic power microsensors

Rendina et al. recently proposed the original configuration of an electromagnetic power sensor for microwaves and millimeter waves that is based on an optically interrogated all-silicon chip [Electron. Lett. 35, 1748 (1999)]. Here we theoretically analyze and discuss in detail the performances of such a new class of nonperturbing and wideband probe in terms of sensitivity, resolution, intrinsic detectivity, linearity, and response time. Good agreement between theory and experiments is demonstrated. In particular, minimum resolutions of approximately 1 mW/cm2 are obtained at frequencies beyond 10 GHz. The dependence of response on the geometrical and electromagnetic parameters of the sensing element is analyzed, and on this basis the possibility of achieving optimized configurations is discussed.     

Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.     

VLSI circuits for low-power high-speed asynchronous addition

This paper presents a new low-power high-speed fully static CMOS variable-time adder. The VLSI implementation proposed here is based on the statistical carry look-ahead addition technique. The new circuit takes advantage of an innovative way of using a composition of propagate signals and of appropriately designed overlapped execution modules to reduce average addition time, layout area, and power dissipation. A 56-bit adder designed as described here and realized using AMS 0.35-/spl mu/m CMOS standard cells at 3.3V supply voltage shows an average addition time of about 4.3 ns and a maximum power dissipation of only 50 mW at 200-MHz repetitive frequency using a silicon area of less than 0.23 mm/sup 2/.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Amorphous silicon-based guided-wave passive and active devices forsilicon integrated optoelectronics

Waveguides and interferometric light amplitude modulators for application at the 1.3- and 1.55-μm fiber communication wavelengths have been fabricated with thin-film hydrogenated amorphous silicon and its related alloys. The technique adopted for the thin-film growth is the plasma- enhanced chemical vapor deposition, which has been shown to give the lowest defect concentration in the film. Consequently the proposed waveguiding structures take advantage of the low optical absorption shown by a-Si:H at photon energies below the energy gap. In addition a good radiation confinement can be obtained thanks to the bandgap tailoring opportunity offered by this simple and inexpensive technology. In particular rib waveguides, based on a a-SiC:H/a-Si:H stack, have been realized on crystal silicon, showing low propagation losses. Recently, however, a new interest as low as 0.7 dB/cm. The same structure has been utilized for the fabrication of thermooptic Fabry-Perot modulators with switching times of 10 μs. Modulators based on the alternative waveguiding configuration ZnO/a-Si:H, giving comparable results, are also presented     

Time-domain model for power dissipation of CMOS buffers drivinglossy lines

The dynamic power consumption of a CMOS buffer driving lossless and lossy transmission lines is investigated. A time-domain model for power dissipation in both the line driver and the interconnect losses is also presented. The model fully agrees with HSPICE simulations and is particularly suitable for implementation in CAD tools for fast estimation of VLSI dissipation circuits     

An efficient self-timed adder realized using conventional CMOS standard cells

Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 μm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.     

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. However, the additional activities performed to enter and to exit the sleep mode also lead to higher dynamic energy. Our study demonstrates that, due to this, the overall energy consumption achieved by the known low-leakage techniques is greater than the conventional approach. In the second part of this paper, a novel low-leakage SRAM cell is presented. The proposed structure establishes when to enter and to exit the sleep mode, on the basis of the data stored in it, without introducing time and energy penalties with respect to the conventional 6-T cell. The new SRAM structure was realized using the UMC 0.18-mum, 1.8-V, and the ST 90-nm 1-V CMOS technologies. Tests performed with a set of SPEC2000 benchmarks have shown that the proposed approach is actually energy efficient