A hardware solution for real-time intelligent fingerprint acquisition

The first step in any fingerprint recognition system is the fingerprint acquisition. A well-acquired fingerprint image results in high-resolution accuracy and low computational effort of processing. Hence, it is very useful for the recognition system to evaluate recognition confidence level to request new fingerprint samples if the confidence level is low, and to facilitate recognition process if the confidence level is high. This paper presents a hardware solution to ensure a successful and friendly acquisition of the fingerprint image, which can be incorporated at low cost into an embedded fingerprint recognition system due to its small size and high speed. The solution implements a novel technique based on directional image processing that allows not only the estimation of fingerprint image quality, but also the extraction of useful information (in particular, singular points). The digital architecture of the module is detailed and their features in terms of resource consumption and processing speed are illustrated with implementation results into FPGAs from Xilinx. Performance of the solution has been verified with fingerprints from several standard databases that have been acquired with sensors of different sizes and technologies (optical, capacitive, and thermal sweeping).     

Implementation of CMOS fuzzy controllers as mixed-signal integratedcircuits

This paper discusses architectural and circuit-level aspects related to hardware realizations of fuzzy controllers. A brief overview on fuzzy inference methods is given focusing on chip implementation. The singleton or zero-order Sugeno's method is chosen since it offers a good tradeoff between hardware simplicity and control efficiency. The CMOS microcontroller described herein processes information in the current-domain, but input-output signals are represented as voltage to ease communications with conventional control circuitry. Programming functionalities are added by combining analog and digital techniques, giving rise to a versatile microcontroller, capable of solving different control problems. After identifying the basic component blocks, the circuits used for their implementation are discussed and compared with other alternatives. This study is illustrated with the experimental results of prototypes integrated in different CMOS technologies     

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi‐input multi‐output (MIMO) piecewise‐affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90‐nm complementary metal‐oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high‐performance and minimum unitary cost are required. Copyright © 2015 John Wiley & Sons, Ltd.     

Self-checking current-mode analogue memory

A long-term analogue memory based on continuous-time, current-mode algorithmic A/D-D/A converters is presented. It achieves an efficient performance in terms of speed, resolution, power, and area, while incorporating a self-checking ability. Its operation is described and illustrated with experimental results of a CMOS 2.4 μm prototype with 7 bit resolution     

Mixed-signal design of a fully parallel fuzzy processor

The authors present a novel architecture for implementing general-purpose fuzzy chips which allows fully-parallel rule processing employing a reduced number of mixed-signal computing blocks and minimum-sized digital memories. The resulting fuzzy processor can interact directly with continuous sensors and actuators and the subsequent digital processing system     

Integrated circuit implementation of fuzzy controllers

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno's method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 b is achieved. The connection of these blocks according to a proposed architecture allows fuzzy chips with low silicon area whose inference speed is in the range of 2 Mega FLIPS (fuzzy logic inferences per second),     

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.     

Extending the functionality of a flexible current-mode CMOS circuit

A current-mode cell based on the square-law characteristic of MOS transistors in saturation is revisited to extend its functionality. The original structure was reported to provide a squaring operation. However, by biasing the circuit differently the circuit can perform the inverse operation and operate as a geometric-mean/square-rooter. This is illustrated with experimental results     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

Waterbirds and nutrient enrichment in Mar Menor Lagoon, a shallow coastal lake in southeast Spain

The Mar Menor, a 135‐km² saline lake, is the largest water surface on the western Mediterranean coast, and an internationally important bird area. It is surrounded by a large irrigated agricultural plain, with dense tourism developments. Although the impacts of these activities on water quality are locally evident, their effects on waterbird populations are poorly known. In the winter 2004–2005, we studied the distribution of four waterbird species (Podiceps cristatus, Podiceps nigricollis, Phalacrocorax carbo and Fulica atra) around the main drainage channel that discharges into the lake, where it was feasible to infer spatial patterns of eutrophication (alongshore and shore centre) from previous environmental surveys. Waterbirds were counted along a stretch of undeveloped shoreline extending southwards from the channel outlet, in contiguous sections, and in bands parallel to the shoreline. Linear mixed models (LMM) indicated the population density increased only markedly for grebes (Podiceps cristatus, Podiceps nigricollis) and coot (Fulica atra) in littoral bands qualifying as eutrophic, but not an alongshore response, with their finescale alongshore distribution being apparently unrelated to nutrient sources. Considering the whole lake, however, the temporal trends and distribution of the wintering populations indicated that waterbirds respond numerically, in a guild‐specific way, to nutrient inputs. Grebes and coot could be a useful ‘two‐stage’ warning signal for potential problem areas affected by similar influences.