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We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4×4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 104/cm2 seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation  相似文献   
3.
The paper presents the inelastic post-buckling analysis of truss structures by the Dynamic Relaxation (DR) method. A simplified inelastic finite element formulation for truss element and new algorithms are proposed for Elastic Post-Buckling (EPB) analysis and Inelastic Post-Buckling (IEPB) analysis using the DR method. The post-buckling paths for elastic, EPB and IEPB analyses are completely traced using the variable-arc-length method. Four numerical examples are presented to illustrate the application of the proposed algorithms.  相似文献   
4.
Multicasting is becoming increasingly important in today's networks. In optical networks, optical splitters facilitate the multicasting of optical signals. By eliminating the transmission of redundant traffic over certain links, multicasting can improve network performance. However, in a wavelength-division multiplexed (WDM) optical network, the lack of wavelength conversion necessitates the establishment of a single multicast circuit (light-tree) on a single wavelength. On the other hand, establishing several unicast connections (lightpaths) to satisfy a multicast request, while requiring more capacity, is less constrained in terms of wavelength assignment. The objective of the paper is to evaluate the tradeoff between capacity and wavelength continuity in the context of optical multicasting. To this end, we develop accurate analytical models with moderate complexity for computing the blocking probability of multicast requests realized using light-trees, lightpaths, and combinations of light-trees and lightpaths. Numerical results indicate that a suitable combination of light-trees and lightpaths performs best when no wavelength conversion is present.  相似文献   
5.
The microstructure of titania-added Mg-partially-stabilized zirconia (PSZ) is dramatically influenced by thermal treatments. Effects of various sintering, heat-treatment and thermal shock cycling parameters on the microstructure of the Mg-Ti-PSZ system are described. Conditions favourable for the growth of needle-like Ti-rich reinforcements in highly thermalshock-resistant Mg-Ti-PSZ ceramics are identified. TiO2 seems to play a catalytic role in the formation of Zr-rich networks during high-temperature (1700°C) sintering of the Mg-Ti-PSZ system, quite similar to those found in Mg-PSZ, heat-treated above 1300 °C.  相似文献   
6.
HotSpot: a compact thermal modeling methodology for early-stage VLSI design   总被引:3,自引:0,他引:3  
This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.  相似文献   
7.
This paper examines the effect of reference prices on companies operating within competitive industries. We confirm that even with competition, firms optimally price high in the short term to generate a high reference price and then decrease this price over time. Competitors' prices converge toward each other over time, emphasizing the short‐term nature of reference prices. We then show that pricing optimally to take advantage of reference prices generates a positive externality for other firms in an industry, such that competitors may generate higher profit. The longer the focus of a given firm, the more profit the firm generates, but less relative to its competitors. This arises because the externalities created through pricing high to increase reference prices outweigh the benefits of the higher reference prices themselves. If pricing managers are compensated relative to their competition, this suggests that short‐termism may be implicitly encouraged to the detriment of profit.  相似文献   
8.
Complex parallel applications can often be modeled as directed acyclic graphs of coarse-grained application tasks with dependences. These applications exhibit both task and data parallelism, and combining these two (also called mixed parallelism) has been shown to be an effective model for their execution. In this paper, we present an algorithm to compute the appropriate mix of task and data parallelism required to minimize the parallel completion time (makespan) of these applications. In other words, our algorithm determines the set of tasks that should be run concurrently and the number of processors to be allocated to each task. The processor allocation and scheduling decisions are made in an integrated manner and are based on several factors such as the structure of the task graph, the runtime estimates and scalability characteristics of the tasks, and the intertask data communication volumes. A locality-conscious scheduling strategy is used to improve intertask data reuse. Evaluation through simulations and actual executions of task graphs derived from real applications and synthetic graphs shows that our algorithm consistently generates schedules with a lower makespan as compared to Critical Path Reduction (CPR) and Critical Path and Allocation (CPA), two previously proposed scheduling algorithms. Our algorithm also produces schedules that have a lower makespan than pure task- and data-parallel schedules. For task graphs with known optimal schedules or lower bounds on the makespan, our algorithm generates schedules that are closer to the optima than other scheduling approaches.  相似文献   
9.
We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 × 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.  相似文献   
10.
Wireless Personal Communications - The climate has changed absolutely in every area in just a few years as digitized, making high-speed internet service a significant need in the future. Future...  相似文献   
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