A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

A wide range delay locked loop for low power and low jitter applications

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.