Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems

Multi-objective evolutionary algorithms (MOEAs) have received increasing interest in industry because they have proved to be powerful optimizers. Despite the great success achieved, however, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before an acceptable solution can be found. There are, in fact, several industrial situations in which fitness evaluations are computationally expensive and the time available is very short. In these applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performance and efficiency. This is the case in designing a complex embedded system, where it is necessary to define an optimal architecture in relation to certain performance indexes while respecting strict time-to-market constraints. This activity, known as design space exploration (DSE), is still a great challenge for the EDA (electronic design automation) community. One of the most important bottlenecks in the overall design flow of an embedded system is due to simulation. Simulation occurs at every phase of the design flow and is used to evaluate a system which is a candidate for implementation. In this paper we focus on system level design, proposing an extensive comparison of the state-of-the-art of MOEA approaches with an approach based on fuzzy approximation to speed up the evaluation of a candidate system configuration. The comparison is performed in a real case study: optimization of the performance and power dissipation of embedded architectures based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results of the comparison demonstrate that the fuzzy approach outperforms in terms of both performance and efficiency the state of the art in MOEA strategies applied to DSE of a parameterized embedded system.     

A GA-based design space exploration framework for parameterized system-on-a-chip platforms

The constant increase in levels of integration and reduction in the time-to-market has led to the definition of new methodologies, which lay emphasis on reuse. One emerging approach in this context is platform-based design. The basic idea is to avoid designing a chip from scratch. Some portions of the chip's architecture are predefined for a specific type of application. This implies that the basic micro-architecture of the implementation is essentially "fixed," i.e., the principal components should remain the same within a certain degree of parameterization. Many researchers predict that platforms will take the lion's share of the integrated circuit market. In this paper, we propose an approach based on genetic algorithms for exploring the design space of parameterized system-on-a-chip (SOC) platforms. Our strategy focuses on exploration of the architectural parameters of the processor, memory subsystem and bus, making up the hardware kernel of a parameterized SOC platform for the design of embedded systems with strict power consumption and performance constraints. The approach has been validated on two different parameterized architectures: one based on a RISC processor and another based on a parameterized very long instruction word architecture. The results obtained on a suite of benchmarks for embedded applications are discussed in terms of both accuracy and efficiency. As far as accuracy is concerned, the approach gives solutions uniformly distributed in a region less than 1% from the Pareto-optimal front. As regards efficiency, the exploration times required by the approach are up to 20 times shorter than those required by one of the most efficient and widely referenced approaches in the literature.     

An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks

In this paper, we propose an optimized, search based near-optimal mapping heuristic, named as ONMAP for mapping real time embedded application workloads on 2D based on-chip interconnection network platforms. ONMAP exploits NMAP, a well-known and fast nearest neighbor heuristic algorithm by using the modular exact optimization method. The proposed hybrid algorithm minimizes the on-chip inter-processor communication energy consumption and optimizes the interconnection network performance parameters. The algorithm inherits the constructive search based heuristic nature of the NMAP algorithm, as well as the property of exact optimization for mapping embedded applications on the target communication architecture. To verify the efficiency and effectiveness of the algorithm, we have compared the proposed algorithm with NMAP and random mapping algorithm under similar simulation environments and traffic conditions. The mapping results of the exemplary real world applications such as VOPD, PIP, MPEG4, MWD, MMS and WiFi-80211arx indicate that ONMAP algorithm is more efficient than its competitors for most of the performance parameters of the on-chip network designs. The algorithm successfully optimized the energy consumption, up to 20 % and 26% in comparison to NMAP and random algorithms, respectively. Similarly, the cost is optimized up to 10% and 60% as compared to NMAP and random mapping algorithms, respectively.     

Application Specific Routing Algorithms for Networks on Chip

In this paper we present a methodology to develop efficient and deadlock free routing algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or a set of concurrent applications. The proposed methodology, called Application Specific Routing Algorithm (APSRA), exploits the application specific information regarding pairs of cores which communicate and other pairs which never communicate in the NoC platform to maximize communication adaptivity and performance. The methodology also exploits the known information regarding concurrency/non-concurrency of communication transactions among cores for the same purpose. We demonstrate, through analysis of adaptivity as well as simulation based evaluation of latency and throughput, that algorithms produced by the proposed methodology give significantly higher performance as compared to other deadlock free algorithms for both homogeneous as well as heterogeneous 2D mesh topology NoC systems. For example, for homogeneous mesh NoC, APSRA results in approximately 30% less average delay as compared to Odd-Even algorithm just below saturation load. Similarly the saturation load point for APSRA is significantly higher as compared to other adaptive routing algorithms for both homogeneous and non-homogeneous mesh networks.     

Impact of the inversion time on regional brain perfusion estimation with clinical arterial spin labeling protocols

Objective

Evaluating the impact of the Inversion Time (TI) on regional perfusion estimation in a pediatric cohort using Arterial Spin Labeling (ASL).

Materials and methods

Pulsed ASL (PASL) was acquired at 3 T both at TI 1500 ms and 2020 ms from twelve MRI-negative patients (age range 9–17 years). A volume of interest (VOIs) and a voxel-wise approach were employed to evaluate subject-specific TI-dependent Cerebral Blood Flow (CBF) differences, and grey matter CBF Z-score differences. A visual evaluation was also performed.

Results

CBF was higher for TI 1500 ms in the proximal territories of the arteries (PTAs) (e.g. insular cortex and basal ganglia — P < 0.01 and P < 0.05 from the VOI analysis, respectively), and for TI 2020 ms in the distal territories of the arteries (DTAs), including the watershed areas (e.g. posterior parietal and occipital cortex — P < 0.001 and P < 0.01 from the VOI analysis, respectively). Similar differences were also evident when analyzing patient-specific CBF Z-scores and at a visual inspection.

Conclusions

TI influences ASL perfusion estimates with a region-dependent effect. The presence of intraluminal arterial signal in PTAs and the longer arterial transit time in the DTAs (including watershed areas) may account for the TI-dependent differences. Watershed areas exhibiting a lower perfusion signal at short TIs (~ 1500 ms) should not be misinterpreted as focal hypoperfused areas.

     

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

3-D Networks-on-Chip(NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips(MPSoCs).Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging,as the arrival order and task graphs of the target applications are typically not known a priori,which can be further complicated by stringent energy requirements for NoC systems.This paper thus presents an energy-aware run-time incremental mapping algorithm(ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores,while reducing the fragmentation effect on the incoming applications to be mapped,and simultaneously satisfying the thermal constraints imposed on each incoming application.Specifically,incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing.Fragment tiles due to system fragmentation can be gleaned for better resource utilization.Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM,and the results are compared against the optimal mapping algorithm(branch-and-bound) and two heuristic algorithms(TB and TL).The experiments show that ERIM outperforms TB and TL methods with significant energy saving(more than 10%),much reduced average response time,and improved system utilization.