A CMOS channel-select filter for a direct-conversion wirelessreceiver

A highly selective and linear switched-capacitor channel-select filter is fabricated in 1-μm CMOS for a direct-conversion wireless receiver operating in the 902-928 MHz ISM band. The filter selects a 230-kHz wide channel and attenuates by at least 50 dB from 320 kHz to 57 MHz. The input IP3 is +30 dBm, the input-referred noise in the passband is 70 nV/√Hz, and the circuit takes 4.6 mA from a 3.3 V supply. Direct subsampling of the 915 MHz RF input signal by the filter front-end is also demonstrated with only a small degradation in linearity. The input noise voltage is halved in a redesign while keeping the current drain unchanged     

Radios for next-generation wireless networks

Next-generation wireless networks will support a wide range of data rates over several frequency bands and require adaptive and programmable system resources. Radio transceivers used in these wireless networks will incorporate self-calibration and full programmability to support their high performance and adaptivity. Low power designs at the circuit architectural, and overall system levels will enable longer battery life for portable devices. Many additional challenges exist in implementing high data rate programmable orthogonal frequency division multiplexing (OFDM) multiple-input/multiple-output (MIMO) radio transceivers that cover different frequency bands, maintain low current consumption, and are low cost. This article is an examination of the challenges in implementing high data rate programmable orthogonal frequency division multiplexing multiple-input/multiple-output radio transceivers that cover different frequency bands, maintain low current consumption, and are low cost.     

A 2.4-GHz CMOS transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset     

A 1 GHz CMOS RF front-end IC for a direct-conversion wirelessreceiver

An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 μm CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

A single-chip 900-MHz spread-spectrum wireless transceiver in1-μm CMOS. II. Receiver design

For pt. I see ibid., vol. 33, no. 4, April 1998. A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is -8.3 dBm. In active mode, the receiver takes 120 mA from 3 V     

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm² of area in a digital 0.13 mum CMOS process of which 0.29 mm² is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.     

A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n)

802.11n is the latest offering from the IEEE standard committee tasked with enabling and enhancing WLAN systems. This standard utilizes several techniques to offer a much larger rate versus range than the legacy WLAN systems. A single-chip multiband direct-conversion CMOS MIMO transceiver (2times2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the draft 802.1 In standard and achieves PHY rates of > 270 Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40 dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8 V supply and with both cores operating, the chip draws 275 mA in RX mode and 280 mA in TX mode.     

A single-chip 900-MHz spread-spectrum wireless transceiver in1-μm CMOS. I. Architecture and transmitter design

A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-μm CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.