Area-efficient FPGA-based FFT processor

A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the 'twiddle factors' sequentially leads to an area saving up to 35% with respect to other cores.     

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner’s timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

In an orthogonal frequency division multiplexing-based wireless local area network receiver there are three operations that can be performed by a unique coordinate rotation digital computer (CORDIC) processor since they are needed in different time instants. These are the rotation of a vector, the computation of the angle of a vector and the computation of the reciprocal. This paper proposes a common architecture of CORDIC algorithm suitable to implement the three operations with a reduced increase of the hardware cost with respect to a single operation CORDIC. The proposed architecture has been validated on field programmable gate-arrays devices and the results of the implementation show that area saving around 28% and throughput increment of 64% are obtained.

Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder

This paper describes the design of a soft decision Viterbi Decoder for orthogonal frequency division multiplexing-based wireless local area networks and evaluates different architectural options by means of their field programmable gate-array (FPGA) implementation. A finite precision analysis has been performed to reduce the data-path widths under the specifications of IEEE 802.11a and Hiperlan/2 standards. Four implementation strategies (register exchange, trace back, trace back with double rate memory read and pointer trace back) for the survivor management unit have been evaluated together with two different normalization methods for the add–compare–select unit. The results of the implementation in FPGA have been given and it is shown that register exchange and pointer trace back architectures with pre-normalization in the add–compare–select unit achieve the best performance. Both architectures can decode 200 Mbps in a Virtex-4 device with lower latency that the conventional trace back one and pointer trace back exhibits the lowest power consumption, these characteristics make them suitable for future multiple-output multiple-input WLAN systems.

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm². Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10⁻⁵.     

Efficient pipeline FFT processors for WLAN MIMO-OFDM systems

The most area-efficient pipeline FFT processors for WLAN MIMO-OFDM systems are presented. It is shown that although the R2/sup 3/SDF architecture is the most area-efficient approach for implementing pipeline FFT processors, RrMDC architectures are more efficient in MIMO-OFDM systems when more than three channels are used.     

Digit-Serial Complex-Number Multipliers on FPGAs

This paper presents an optimized implementation on FPGA of digit-serial Complex-Number Multipliers (CMs) using Booth recoding techniques and tree adders based on Carry Save (CS) and Ripple Carry Adders (RCA). This kind of Complex-Number multipliers can be pipelined at the same level independent of the digit-size. Variable and fixed coefficient CMs have been considered. In the first case an efficient mapping of the modified Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5:3 and 4:3 converters in the CS structure and the utilization of RCA trees lead to a minimum area requirement. In the case of fixed coefficient CMs, partial products generator is based on look-up tables and multi-bit Booth recoding is used to reduce the area and increase the performance of the circuit. The study reveals that efficient mapping of the 5-bit Booth recoding to generate the partial products is the optimum multibit recoding when Xilinx FPGA devices are used.     

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

This paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture which overlaps the check-node and variable-node update stages, achieving a good tradeoff between area and throughput, and also, high hardware utilization efficiency (HUE). The proposed modification does not affect the performance of the SMP algorithm and yields an area reduction of 33%. As an example, SMP architecture and the proposed modification was synthesized in a 90 nm CMOS process for the 2048-bit LDPC code of the IEEE802.3an standard with 16 iterations achieving a throughput of 5.9 Gbps with 15.3 mm² and 6.2 Gbps with 10.2 mm², respectively.     

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency.

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.