Tunneling in field induced diode in indium antimonide

Tunneling in the forward bias polarity of a field induced diode in indium antimonide is treated theoretically and experimentally. The theory leads to tunneling current-voltage characteristics with a region of negative resistance which are dependent upon the various parameters of the device, such as the gate voltage, substrate acceptor concentration and oxide thickness. A three-terminal device in which the gate voltage controls the tunneling I–V characteristics can thus be realized.Measurements were performed on an experimental device obtained by diffusion of cadmium into N-type InSb semiconductor. A chemically deposited SiO₂ layer was used to isolate the evaporated CrAu gate electrode from the substrate. Deviations from theory are shown to result from the two-dimensional character of the device.     

Thin films of ZrO2 metal organic chemical vapor deposition

ZrO₂ layers were deposited for the purpose of obtaining high dielectric constant insulating layers for capacitance applications. Trifluoroacety lacetonate of zirconium was used as the source material in our open MOCVD system. Layer thickness was in the range 300–1500 Å, the substrate being degenerate n-type silicon wafers. Under optimum conditions layers with good adhesion and uniformity were obtained. The layers were polycrystalline with characteristic linear dimensions of 400 Å. Electrical measurements were used for characterization and the relative dielectric constants obtained were 30 ± 1.     

Spine-shaped gold protrusions improve the adherence and electrical coupling of neurons with the surface of micro-electronic devices

Interfacing neurons with micro- and nano-electronic devices has been a subject of intense study over the last decade. One of the major problems in assembling efficient neuro-electronic hybrid systems is the weak electrical coupling between the components. This is mainly attributed to the fundamental property of living cells to form and maintain an extracellular cleft between the plasma membrane and any substrate to which they adhere. This cleft shunts the current generated by propagating action potentials and thus reduces the signal-to-noise ratio. Reducing the cleft thickness, and thereby increasing the seal resistance formed between the neurons and the sensing surface, is thus a challenge and could improve the electrical coupling coefficient. Using electron microscopic analysis and field potential recordings, we examined here the use of gold micro-structures that mimic dendritic spines in their shape and dimensions to improve the adhesion and electrical coupling between neurons and micro-electronic devices. We found that neurons cultured on a gold-spine matrix, functionalized by a cysteine-terminated peptide with a number of RGD repeats, readily engulf the spines, forming tight apposition. The recorded field potentials of cultured Aplysia neurons are significantly larger using gold-spine electrodes in comparison with flat electrodes.     

Measurement of Fowler-Nordheim tunneling currents in MOS structures under charge trapping conditions

The Fowler-Nordheim (FN) tunneling of electrons into thermal SiO₂ at high levels of injection has been studied. A modified I–V measurement technique has been developed to correct for charge trapping phenomena, which are unavoidable under the high field and current conditions. It is shown that the results fit a universal FN type current-field dependence which is insensitive to oxide thickness and free of the commonly observed hysteresis phenomena.     

Pyramid-shaped silicon photodetector with subwavelength aperture[for NSOM]

We present a new type of silicon photodetector with a subwavelength aperture designed to scan material surfaces with a resolution inaccessible by conventional optical microscopy. Such a probe is designed for integration into a near-field scanning optical microscope (NSOM) for scanning and collecting information from the near-field region located at the vicinity of the surface. The photodetector, which was realized by conventional microelectronics technology, is located on top of a 250-μm-high pyramid, enabling detection of reflected as well as transmitted light. The light sensitive part of the probe consists of a micromachined silicon structure built using anisotropic etch solutions such as ethylene diamine pyrocatechol (EDP) and KOH. The shape of the probe is a truncated double pyramid with a ring shape top silicon/aluminum Schottky diode surrounding an exposed silicon photosensitive area of about 150 nm in diameter. Typical I-V characteristics and optical response measurements are presented     

VLSI implementation of pulse activated synapses

A generic circuit, the pulse stimulated charge pumping (PSCP) synapse, is presented. The PSCP synapse is a device based on charge pumping of interface states: it produces at its output a charge packet proportional to the number of pulses applied to its input, and to the electrically programmed density of interface states. It is particularly suitable for realising artificial neural networks in which the neuron activity is implemented as a pulse train, closely resembling the behaviour of biological neural networks. The PSCP synapse can be realised easily in less than 50 mu m/sup 2/, and has a large dynamic range. Preliminary experimental results are presented showing the current against frequency behaviour of the device, for various densities of interface states.<>     

Data retention reliability model of NROM nonvolatile memory products

Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.     

Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.     

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.