Preparation of Silver Nanowires via a Rapid,Scalable and Green Pathway

Rapid synthesis of silver nanowires(Ag NWs) with high quality and a broad processing window is challenging because of the low selectivity of the formation of multiply twinned particles at the nucleation stage for subsequent Ag NWs growth.Herein we report a systematic study of the water-involved heterogeneous nucleation of Ag NWs with high rate(less than 20 min) in a simple and scalable preparation method.Using glycerol as a reducing agent and a solvent with a high boiling point,the reaction is rapidly heated to 210 ℃ in air to synthesize Ag NWs with a very high yield in gram level.It is noted that the addition of a small dose of water plays a key role for obtaining highly pure Ag NWs in high yield,and the optimal water/glycerol ratio is0.25%.After investigating a series of forming factors including reaction temperature and dose of catalysts,the formation kinetics and mechanism of the Ag NWs are proposed.Compared to other preparation methods,our strategy is simple and reproducible.These Ag NWs show a strong Raman enhancement effect for organic molecules on their surface.     

LDD方法在提高电路工作电压中的应用研究

研究了利用轻掺杂漏结构来制作高电源电压器件的工艺方法。分析了ＬＤＤ结构参数对器件击穿特性的影响，并结合实验结果对Ｎ＾－区的注入剂量，长度及引入的串联电阻进行了优化设计。     

NMOS器件两次沟道注入杂质分布和阈电压计算

分别考虑了深浅两次沟道区注入杂质在氧化扩散过程中对表面浓度的贡献。对两次注入杂质的扩散分别提取了扩散系数的氧化增强系数、氧化衰减系数和有效杂地系数，给出了表面浓度与工艺参数之间的模拟关系式，以峰值浓度为强反型条件计算了开启电压，文章还给出了开启电压、氧化条件、不同注入组合之间的关系式。     

深亚微米MOSFET衬底电流的模拟与分析

利用器件模拟手段对深亚微米ＭＯＳＦＥＴ的衬底电流进行了研究和分析，给出了有效的道长度，栅氧厚度，源漏结深，衬底掺杂浓度以及电源电压对深亚微米ＭＯＳＦＥＴ衬底电流的影响，发现电源电压对深亚微米ＭＯＳＦＥＴ的衬底电流有着强烈的影响，热载流子效应随电源电压的降低而迅速减小，当电源电压降低到一定程度时，热载流子效应不再成为影响深亚微米ＭＯＳ电路可靠性的主要问题。     

一种RISC单片机的分块结构寄存器堆

介绍了一种用于ＲＩＳＣ单片机ＰＩＣ１６Ｃ５７的寄存器堆，讨论了为降低功耗所采用的分块结构，详细说明了译码逻辑、ＳＲＡＭ单元、读／写电路和文件选择寄存器等电路的形式及其工作原理     

一种密钥管理的新方案

本文提出了一种新的4级密钥管理方案.该方案通过一个密码操作核心的精心设计,为各用户使用系统的各种功能提供了方便的手段,同时确保了系统的安全性.此外,该方案还大大降低了系统开发费用和保密通信的复杂度.因此,该方案克服了以往方案中的缺陷,已被正在开发的系统SUTU采用.     

提高E^2PROM中NMOS管源漏穿通电压的实验研究

为了提高Ｅ＾２ＰＲＯＭ中Ｎ管源漏穿通电压，用实验的方法对制造工艺进行了研究。结果表明，高能量注入是提高ＶＰＴ的有效手段，但受到ｐｎ结击穿的限制，只适用于低区短沟Ｎ管；ＤＤＤ工艺大幅度高ＶＰＴ，但ｐｎ结击穿电压低于２０Ｖ，不能应用于高压ＭＯＳ管；采用适量的防穿通注入和适当增大沟道长度为最理想的工艺途径。     

多目标多约束的集成电路统计优化策略

对于集成电路设计、生产过程中的多目标、多约束统计优化问题,本文提出了“合格率足够高”的优化宗旨,并从概率论的基本原理出发,结合集成电路的特点,导出了一种合格率的近似表述方法,提出的变权重Monte Carlo法编程简便,效率高。采用这些优化策略设计的集成电路合格率优化系统取得了比较好的结果。     

APPLICATION OF MOLECULAR ORBITAL THEORY TO ANALYSIS OF PHASE STABILITY FOR ALLOYS

The critical _d vahues ( _ ) of the γ/(γ+σ).γ/(γ+μ) and γ/(γ+γ') phase boundaries insome ternar alloy phase diagrams at various temperatures are calculated by averaging the _d values of sererai selected characteristic points at the phase boundaries.Approxmateequations for the temperature dependence of the critical _d of γ/(γ+σ).γ/(γ+μ) andγ/(γ+γ') phase boundaries are established.The accuracy of the analysis is discussed in detail.It is found for the first time that the average value of the bondorder _ at the phase boundaries ts also approximatelr a constant and therefore a criticalaverage bond order _ like - can be introduced for the analysts of phase stability     

IN-SITU OBSERVATION OF CRACK TIP DEFORMATION IN A DUPLEX STAINLESS STEEL

The development of dislocation structures in the plastic zone ahead of a crack tip has been in-vestigated in a duplex stainless steel during in-situ deformation experiments in a scanningtransmission electron microscope.It was found that the dislocation distribution wassignificantly different in the ferrite and in the austenite.In the ferrite grains,the dislocationsemitted by the crack tip may cross-slip out of the original slip planes and form a broad plasticzone.However,in the austenite,the dislocation free zone is small and the dislocations emittedby the crack pile up in its slip plane.The selection of slip systems at the crack tip depends onthe crack tip Schmid factors in both phases.But after large deformation,the selection of thesecond slip systems at the craek tip in austenite does not depend on the Schmid factors.