A scalable and low power VLIW DSP core for embedded system design

Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set （VLES） execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product.     

2,5-二甲氧基氯苯的合成

以对苯醌为原料,通过氯化和甲基化两步合成2,5-二甲氧基氯苯,总收率达到78%。在35℃下对苯醌在二氯乙烷和盐酸两相体系中催化合成2,5-二羟基氯苯,收率89%。所得到的2,5-二羟基氯苯再在碱性条件下用硫酸二甲酯甲基化合成2,5-二甲氧基氯苯。中间体和目标产物分别由IR和GC-MS分析,结构正确,产品纯度大于98%。     

一种适用于低功耗超长指令字DSP处理器的硬件循环缓冲设计

提出了用于VLI WDSP处理器的硬件循环缓冲器的设计.该DSP处理器在结构上利用了在信号处理程序中循环经常出现这一特点,专门设计了硬件循环处理模块用来消除因循环跳转造成的流水线等待,以达到循环的零开销处理从而提高DSP的性能.设计过程中为了减小硬件开销,对循环的长度特点进行了分析,把循环分类两类并用不同的方法处理.结果表明循环跳转的处理是在独立模块中操作,没有造成流水线的等待提高了性能,该硬件循环的面积是3 .8 k逻辑门.