Robust resource allocation in a cluster based imaging system

Recently there has been an increased demand for imaging systems in support of high-speed digital printing. The required increase in performance in support of such systems can be accomplished through an effective parallel execution of image processing applications in a distributed cluster computing environment. The output of the system must be presented to a raster based display at regular intervals, effectively establishing a hard deadline for the production of each image. Failure to complete a rasterization task before its deadline will result in an interruption of service that is unacceptable. The goal of this research was to derive a metric for measuring robustness in this environment and to design a resource allocation heuristic capable of completing each rasterization task before its assigned deadline, thus, preventing any service interruptions. We present a mathematical model of such a cluster based raster imaging system, derive a robustness metric for evaluating heuristics in this environment, and demonstrate using the metric to make resource allocation decisions. The heuristics are evaluated within a simulation of the studied raster imaging system. We clearly demonstrate the effectiveness of the heuristics by comparing their results with the results of a resource allocation heuristic commonly used in this type of system.     

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

Integrated antennas on silicon substrates for communication over free space

This letter reports the feasibility of using 2-mm-long on-chip antennas for communication over free space. Integration of antennas into radio frequency integrated circuits (RFICs) eliminates external transmission line connections and sophisticated packaging, which should lower the cost of wireless systems operating above 10 GHz. Mobile microwave probe stands have been developed for measurements at varying antenna pair separations. Antenna-pair gains for 2-mm-long integrated zigzag dipole antennas fabricated on 20-/spl Omega/-cm silicon substrates have been characterized near 24 GHz for separations up to 15 m. The antenna-pair gains show R/sup -2/ dependence up to /spl sim/4-5 m. The antennas were found to be sufficient for use up to 5 m and possibly larger separations.     

Communication Using Antennas Fabricated in Silicon Integrated Circuits

The feasibility of integrating compact antennas and required circuits for implementing wireless interconnections in foundry digital CMOS technologies has been demonstrated. A 3-mm long zigzag dipole antenna on a 20-Omega-cm substrate should have efficiency up to approximately 25% at 24 GHz and cost 1-2 cents. These antennas can be used to implement a radio for 100-kb/s communication up to about 10 m. By lowering the operation frequency to 5.8 GHz and using a monopole structure, which occupies approximately 30% more area, the communication range can be increased by three times or more. This technology, as well as in a true single-chip radio, can be used for intra- and inter-chip data communication, intra- and inter-chip clock distribution, beacons, radars, RFID tags, and contactless high-frequency testing.     

On-chip antennas in silicon ICs and their application

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others.     

Robust static allocation of resources for independent tasks under makespan and dollar cost constraints

Heterogeneous computing (HC) systems composed of interconnected machines with varied computational capabilities often operate in environments where there may be inaccuracies in the estimation of task execution times. Makespan (defined as the completion time for an entire set of tasks) is often the performance feature that needs to be optimized in such systems. Resource allocation is typically performed based on estimates of the computation time of each task on each class of machines. Hence, it is important that makespan be robust against errors in computation time estimates. In this research, the problem of finding a static mapping of tasks to maximize the robustness of makespan against the errors in task execution time estimates given an overall makespan constraint is studied. Two variations of this basic problem are considered: (1) where there is a given, fixed set of machines, (2) where an HC system is to be constructed from a set of machines within a dollar cost constraint. Six heuristic techniques for each of these variations of the problem are presented and evaluated.     

RF subsystems implemented in mainstream CMOS - Overcoming special concerns affecting performance and cost

Research is underway to explore the feasibility of implementing complete RF subsystems in standard mainstream CMOS processes without a need for any off-chip components. Progress to date has verified that RF circuits and on-chip antennas adequate for chip to chip communication can be realized, and it can be stated with some certainty that feasibility has been established. Radio architecture, signaling methodology, and individual circuit blocks have been devised and confirmed. It remains to demonstrate an on-chip reference with +/-150 ppm stability, optimize the individual circuit blocks, and demonstrate the overall concept in a single integrated chip     

Quantitative Characterization of Corrosion Under Insulation

A method is described to quantitatively characterize the corrosion status of steel samples under insulation. The method uses backscatter X-rays to obtain a density vs. depth profile of the sample, from which the mass absorption coefficient, density, and thickness of the rust layer are evaluated. From these data, the iron content of the rust layer is computed, and the steel losses are expressed in either wall thickness or in the mass per unit area. Rust with a thickness of less than 1 mm can be detected but not quantified. The upper limit for quantitative expression of steel losses is approximately 6 mm when an X-ray tube operated at 160 KV is used.