Full AC analysis of value of DER to the grid and optimal DER scheduling

This paper presents part of the work ComEd and Quanta Technology have performed to quantify the locational and temporal value of DER to avoid distribution grid upgrade investments. It focuses on the formulation of a robust and efficient algorithm for DER optimal dispatch on a distribution feeder to mitigate the violation of current and voltage limits using the allocated cost of capacity and locational marginal value of real and reactive DER injection/withdrawal.     

Predicting the Operational Efficiency of High-Pressure Roller Crushers

Russian Engineering Research - Models based on regression analysis for predicting the operational efficiency of high-pressure roller crushers are considered. A systematized and structured...     

Safety Devices Based on Smart Alloys

Journal of Machinery Manufacture and Reliability - A device based on smart alloys has been designed for use in machine building items, in particular, in nuclear engineering, for preventing...     

Probabilistic Analysis of the Reliability and Fatigue Life of Machine Parts by Fatigue Failure

Journal of Machinery Manufacture and Reliability - The problem of calculating the reliability and fatigue life of machine parts by the fatigue failure under random changes in the actual and limit...     

Unsupervised Segmentation of Stereoscopic Video Objects: Constrained Segmentation Fusion Versus Greedy Active Contours

In this paper, we present a novel memory access reduction scheme (MARS) for two-dimension fast cosine transform (2-D FCT). It targets programmable DSPs with high memory-access latency. It reduces the number of memory accesses by: 1) reducing the number of weighting factors and 2) combining butterflies in vector-radix 2-D FCT pruning diagram from two stages to one stage with an efficient structure. Hardware platform based on general purpose processor is used to verify the effectiveness of the proposed method for vector-radix 2-D FCT pruning implementation. Experimental results validate the benefits of the proposed method with reduced memory access, less clock cycle and fewer memory space compared with the conventional implementation.