Carrier multiplication in submicrometre pMOS transistors operated at cryogenic temperatures

The temperature and bias dependence of the carrier multiplication M(I/sub bulk//I/sub drain/) in submicrometre pMOS transistors has been characterised and studied over the temperature range of 30-300 K. In addition, a model which reproduces the bias dependence of M over the measured range of temperature can be extrapolated down to 4.2 K to predict the internal bulk potential and its related 'kink effect'. The agreement between data and the prediction of the model confirms that the gate voltage and temperature dependence of the mean free path plays the key role in determining the carrier multiplication characteristics of submicrometre pMOS transistors, operating in the temperature range of 4.2-300 K.<>     

Relationship between microstructure and mechanical properties of polyether block amide foams

The mechanical behaviors of five polyether block amide foams, obtained by mold-opening foam injection process, were investigated with regard to their microstructures. The materials vary in mass ratios of hard versus soft segments, and/or in process packing time. The resulting microstructures have been characterized in terms of cavity size and shape ratios, by analyzing scanning electron microscope images after careful sample preparation. The foam mechanical responses have been characterized in compression at small and large strain. At small strain, the initial linear part of the stress–strain curve is enhanced firstly by the hard segment mass ratio and secondly by the fineness of the microstructure. Similar results have been obtained at large strain. The foam viscoelasticity at large strain has been characterized by stress relaxation and strain recovery tests, relevant for foam applications. Reduced packing time and pressure have been shown to lead to the presence of undesired large cavities. The morphological defects appear to have a negligible impact on the macroscopic mechanical behavior of the foams at infinitesimal strain, but lead to critical inconsistency at large strain. Furthermore, the mechanical behavior of the tested polyether block amide foams is controlled first by hard versus soft segments ratio, and second by the microstructure fineness.     

Analytical model for the current-voltage characteristics of a silicon resistor at liquid helium temperatures

A simple analytical model for the current-voltage behaviour of a silicon resistor at liquid helium temperature (LHeT) is presented. It is derived from a more sophisticated analysis, taking account of impurity breakdown by impact ionization and of barrier-limited (BL) and space-charge-limited (SCL) current flow. As will be shown, the turn-on/turn-off hysteresis can be understood by considering the slow, ‘forced’ build-up of a depletion region at the injecting contact. Both material-(technology-) related parameters and measurement history determine the injection threshold of the device. This breakdown/hysteresis behaviour is also seen in the characteristics of more ‘complicated’ devices at LHeT and enhances parasitic phenomena in cryogenic circuitry.     

Yttrium incorporation in Cr2AlC: On the metastable phase formation and decomposition of (Cr,Y)2AlC MAX phase thin films

Herein we report on the synthesis of a metastable (Cr,Y)₂AlC MAX phase solid solution by co-sputtering from a composite Cr–Al–C and elemental Y target, at room temperature, followed by annealing. However, direct high-temperature synthesis resulted in multiphase films, as evidenced by X-ray diffraction analyses, room-temperature depositions, followed by annealing to 760°C led to the formation of phase pure (Cr,Y)₂AlC by diffusion. Higher annealing temperatures caused a decomposition of the metastable phase into Cr₂AlC, Y₅Al₃, and Cr-carbides. In contrast to pure Cr₂AlC, the Y-containing phase crystallizes directly in the MAX phase structure instead of first forming a disordered solid solution. Furthermore, the crystallization temperature was shown to be Y-content dependent and was increased by ∼200°C for 5 at.% Y compared to Cr₂AlC. Calculations predicting the metastable phase formation of (Cr,Y)₂AlC and its decomposition are in excellent agreement with the experimental findings.     

Recent Progress in Applications of the Cold Sintering Process for Ceramic–Polymer Composites

Ceramic–polymer composites are of interest for designing enhanced and unique properties. However, the processing temperature windows of sintering ceramics are much higher than that of compaction, extrusion, or sintering of polymers, and thus traditionally there has been an inability to cosinter ceramic–polymer composites in a single step with high amounts of ceramics. The cold sintering process is a low‐temperature sintering technology recently developed for ceramics and ceramic‐based composites. A wide variety of ceramic materials have now been demonstrated to be densified under the cold sintering process and therefore can be all cosintered with polymers from room temperature to 300 °C. Here, the status, understanding, and application of cold cosintering, with different examples of ceramics and polymers, are discussed. One has to note that these types of cold sintering processes are yet new, and a full understanding will only emerge after more ceramic–polymer examples emerge and different research groups build upon these early observations. The general processing, property designs, and an outlook on cold sintering composites are outlined. Ultimately, the cold sintering process could open up a new multimaterial design space and impact the field of ceramic–polymer composites.     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

Two- and three-dimensional calculation of substrate resistance

A two- and three-dimensional solution of the Laplace equation for the calculation of the substrate resistance for rectangular contacts is presented. After the calculations are performed for a uniform substrate, an extension is given to nonuniform doped regions. This solution makes it possible to investigate the influence of buried layers and field implementations on substrate and well resistances     

On the optimisation of outside spacer bipolar transistors for 0.5 μm high performance mixed analog/digital BiCMOS

Contents For high performance mixed analog/digital and ECL-CMOS applications the inside spacer, double poly bipolar structure has attracted most attention. Although this structure offers superior performance over it's outside spacer counterpart, a significant increase in the cost and complexity of the BiCMOS process is incurred especially when combined with trench isolation and composite material inside spacers. In this paper we examine different approaches for enhancing the performance of CMOS compatible outside spacer transistors opening up the possibility for lower complexity, high peformance BiCMOS processes. As a vehicle for this work we report on the integration of outside spacer bipolar transistors in a baseline digital 0.5 m, 3.3 Volt, triple level metal CMOS technology. Transistors with peakf _T (extracted as gain bandwidth) of 17–18 GHz,BV _ceo5 Volts and Early voltageV _A of 25–30 Volts are reported. Future lateral and vertical scaling is expected to yield performance which compares favourably to more complex inside spacer processes.

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Aspekte zur Optimierung von Outside Spacer Bipolartransistoren für eine leistungsfähige 0.5 m BiCMOS-Technologie für Analog-Digitalanwendungen

Übersicht Für leistungsfähige Analog-Digital-sowie ECL-CMOS-Anwendungen haben inside spacer Doppel-Polysilizium Bipolartransistoren die größte Aufmerksamkeit erzielt. Diese Transistoren besitzen, verglichen mit outside spacer Strukturen, hervorragende Eigenschaften. Allerdings beinhaltet diese Technologie eine wesentliche Steigerung der Kosten sowie der Komplexität des BiCMOS-Prozesses, insbesondere wenn Trench-Isolation und Doppellagenspacer angewandt werden. In diesem Artikel werden verschiedene Methoden zur Leistungssteigerung von CMOS-kompatiblen outside spacer Transistoren untersucht, was Möglichkeiten für weniger komplexe, aber leistungsfähige BiCMOS-Prozesse eröffnet. Untersuchungsobjekt für diese Arbeit ist die Integration von outside spacer Bipolartransistoren in eine 0.5 m – 3.3 V-Standard-CMOS-Technologie für Digitalanwendungen mit Dreilagenmetallisierung. Es werden Transistoren mit einer cut-off-Frequenz (Verstärkungs-Bandbreiten-Produkt) von 17–18 GHz, einer Kollektor-Emitter-Durchbruchspannung (BV _ceo) von 5 V und einer Earlyspannung von 25–30 V vorgestellt. Von zukünftigem lataralen und horizontalen scaling werden Transistoreigenschaften erwartet, die sich mit denen von Transistoren der komplexeren inside spacer-Technologien vergleichen lassen.

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This work was carried out with the support of the ESPRIT 8001 TIBIA project. The authors would also like to thank G. Vancuyck and F. Vleugels for stimulating discussions and assistance with measurements and analysis.     

Erratum to: Electrochemical dissolution of metallic platinum in ionic liquids

The electrochemical dissolution of Pt in several ionic liquids (ILs) was studied. Different ILs were tested assessing their potential to dissolve Pt. Dissolution rate and current efficiency were evaluated. The main focus was on Cl containing ILs: first generation, eutectic-based ILs and second generation ILs with discrete anions. Pt dissolution only occurred in type 1 eutectic-based ILs with a max. dissolution rate of 192.2 g m^?2 h^?1 and a max. current efficiency of 99 % for the ZnCl₂–1-ethyl-3-methylimidazolium chloride IL, and 9.090 g m^?2 h^?1 and 96 % for the 1:1 ZnCl₂–choline chloride IL. The dissolution occurred through the formation of [PtCl_x]^y? complexes. To form these complexes, addition of a metal chloride was necessary. Furthermore, an IL with an electrochemical window of 1.5 V, preferably 2.0 V was required to achieve Pt dissolution. The added metal salt needed to have a higher decomposition potential than 1.5 V or should be a Pt salt.